Search

David Ton

Examiner (ID: 3564, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2784, 2782, 2138, 2317, 2133
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4831193 [patent_doc_number] => 20080127356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'EMBEDDED SYSTEMS AND METHODS FOR SECURING FIRMWARE THEREIN' [patent_app_type] => utility [patent_app_number] => 11/563233 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127356.pdf [firstpage_image] =>[orig_patent_app_number] => 11563233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563233
EMBEDDED SYSTEMS AND METHODS FOR SECURING FIRMWARE THEREIN Nov 26, 2006 Abandoned
Array ( [id] => 333158 [patent_doc_number] => 07512856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Register circuit, scanning register circuit utilizing register circuits and scanning method thereof' [patent_app_type] => utility [patent_app_number] => 11/562424 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3759 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512856.pdf [firstpage_image] =>[orig_patent_app_number] => 11562424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562424
Register circuit, scanning register circuit utilizing register circuits and scanning method thereof Nov 21, 2006 Issued
Array ( [id] => 261902 [patent_doc_number] => 07574636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/561023 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8083 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574636.pdf [firstpage_image] =>[orig_patent_app_number] => 11561023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561023
Semiconductor memory device Nov 16, 2006 Issued
Array ( [id] => 294219 [patent_doc_number] => 07546519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Method and apparatus for detecting and correcting soft-error upsets in latches' [patent_app_type] => utility [patent_app_number] => 11/560420 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546519.pdf [firstpage_image] =>[orig_patent_app_number] => 11560420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560420
Method and apparatus for detecting and correcting soft-error upsets in latches Nov 15, 2006 Issued
Array ( [id] => 5105635 [patent_doc_number] => 20070064510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Method And Apparatus For Evaluating And Optimizing A Signaling System' [patent_app_type] => utility [patent_app_number] => 11/559111 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 20252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20070064510.pdf [firstpage_image] =>[orig_patent_app_number] => 11559111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559111
Method and apparatus for evaluating and optimizing a signaling system Nov 12, 2006 Issued
Array ( [id] => 265588 [patent_doc_number] => 07571362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Method of managing fails in a non-volatile memory device and relative memory device' [patent_app_type] => utility [patent_app_number] => 11/557786 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3301 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571362.pdf [firstpage_image] =>[orig_patent_app_number] => 11557786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557786
Method of managing fails in a non-volatile memory device and relative memory device Nov 7, 2006 Issued
Array ( [id] => 4592875 [patent_doc_number] => 07853851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Method and apparatus for detecting degradation in an integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 11/593744 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853851.pdf [firstpage_image] =>[orig_patent_app_number] => 11593744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593744
Method and apparatus for detecting degradation in an integrated circuit chip Nov 5, 2006 Issued
Array ( [id] => 5197899 [patent_doc_number] => 20070297217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD AND CIRCUIT ARRANGEMENT FOR OPERATING A VOLATILE RANDOM ACCESS MEMORY AS A DETECTOR' [patent_app_type] => utility [patent_app_number] => 11/556760 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4701 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20070297217.pdf [firstpage_image] =>[orig_patent_app_number] => 11556760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556760
Method and circuit arrangement for operating a volatile random access memory as a detector Nov 5, 2006 Issued
Array ( [id] => 171921 [patent_doc_number] => 07669089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Multi-level file representation corruption' [patent_app_type] => utility [patent_app_number] => 11/555614 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669089.pdf [firstpage_image] =>[orig_patent_app_number] => 11555614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555614
Multi-level file representation corruption Oct 31, 2006 Issued
Array ( [id] => 106992 [patent_doc_number] => 07730374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Self test circuit for a semiconductor intergrated circuit' [patent_app_type] => utility [patent_app_number] => 11/555524 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 54 [patent_no_of_words] => 9122 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730374.pdf [firstpage_image] =>[orig_patent_app_number] => 11555524 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555524
Self test circuit for a semiconductor intergrated circuit Oct 31, 2006 Issued
Array ( [id] => 600420 [patent_doc_number] => 07437630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Testing a multibank memory module' [patent_app_type] => utility [patent_app_number] => 11/555138 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5462 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437630.pdf [firstpage_image] =>[orig_patent_app_number] => 11555138 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555138
Testing a multibank memory module Oct 30, 2006 Issued
Array ( [id] => 4966871 [patent_doc_number] => 20080109691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Method and Apparatus for Executing a BIST Routine' [patent_app_type] => utility [patent_app_number] => 11/553582 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4284 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109691.pdf [firstpage_image] =>[orig_patent_app_number] => 11553582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553582
Method and Apparatus for Executing a BIST Routine Oct 26, 2006 Abandoned
Array ( [id] => 5273663 [patent_doc_number] => 20090077439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'INTEGRATED CIRCUIT TEST METHOD AND TEST APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/092186 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3066 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077439.pdf [firstpage_image] =>[orig_patent_app_number] => 12092186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/092186
Integrated circuit test method and test apparatus Oct 22, 2006 Issued
Array ( [id] => 4905607 [patent_doc_number] => 20080115021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Plesiochronous transmit pin with synchronous mode for testing on ATE' [patent_app_type] => utility [patent_app_number] => 11/582803 [patent_app_country] => US [patent_app_date] => 2006-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20080115021.pdf [firstpage_image] =>[orig_patent_app_number] => 11582803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582803
Plesiochronous transmit pin with synchronous mode for testing on ATE Oct 17, 2006 Issued
Array ( [id] => 188515 [patent_doc_number] => 07650543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Plesiochronous receiver pin with synchronous mode for testing on ATE' [patent_app_type] => utility [patent_app_number] => 11/582798 [patent_app_country] => US [patent_app_date] => 2006-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/650/07650543.pdf [firstpage_image] =>[orig_patent_app_number] => 11582798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582798
Plesiochronous receiver pin with synchronous mode for testing on ATE Oct 17, 2006 Issued
Array ( [id] => 860510 [patent_doc_number] => 07376885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Memory efficient LDPC decoding methods and apparatus' [patent_app_type] => utility [patent_app_number] => 11/582190 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11855 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376885.pdf [firstpage_image] =>[orig_patent_app_number] => 11582190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582190
Memory efficient LDPC decoding methods and apparatus Oct 16, 2006 Issued
Array ( [id] => 297937 [patent_doc_number] => 07543216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-02 [patent_title] => 'Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture' [patent_app_type] => utility [patent_app_number] => 11/550336 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6359 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543216.pdf [firstpage_image] =>[orig_patent_app_number] => 11550336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550336
Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture Oct 16, 2006 Issued
Array ( [id] => 4895370 [patent_doc_number] => 20080104470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test' [patent_app_type] => utility [patent_app_number] => 11/581142 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6432 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104470.pdf [firstpage_image] =>[orig_patent_app_number] => 11581142 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581142
Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test Oct 11, 2006 Issued
Array ( [id] => 4586975 [patent_doc_number] => 07849374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-07 [patent_title] => 'Testing a transceiver' [patent_app_type] => utility [patent_app_number] => 11/546806 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849374.pdf [firstpage_image] =>[orig_patent_app_number] => 11546806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546806
Testing a transceiver Oct 10, 2006 Issued
Array ( [id] => 280024 [patent_doc_number] => 07558997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Wiring structure and method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/544751 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4622 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558997.pdf [firstpage_image] =>[orig_patent_app_number] => 11544751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544751
Wiring structure and method of semiconductor integrated circuit Oct 9, 2006 Issued
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