
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 265587
[patent_doc_number] => 07571361
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-04
[patent_title] => 'Recording method and optical disk recording device'
[patent_app_type] => utility
[patent_app_number] => 11/652966
[patent_app_country] => US
[patent_app_date] => 2007-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 11402
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/571/07571361.pdf
[firstpage_image] =>[orig_patent_app_number] => 11652966
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/652966 | Recording method and optical disk recording device | Jan 11, 2007 | Issued |
Array
(
[id] => 4550413
[patent_doc_number] => 07873887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-18
[patent_title] => 'Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in test pattern generation program product'
[patent_app_type] => utility
[patent_app_number] => 11/619954
[patent_app_country] => US
[patent_app_date] => 2007-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_words_short_claim] => 81
[patent_maintenance] => 1
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[pdf_file] => patents/07/873/07873887.pdf
[firstpage_image] =>[orig_patent_app_number] => 11619954
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/619954 | Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in test pattern generation program product | Jan 3, 2007 | Issued |
Array
(
[id] => 6565069
[patent_doc_number] => 20100223510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-02
[patent_title] => 'NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND DEFECT MANAGEMENT METHOD FOR NONVOLATILE MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/160972
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 7883
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20100223510.pdf
[firstpage_image] =>[orig_patent_app_number] => 12160972
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/160972 | Nonvolatile memory device, nonvolatile memory system, and defect management method for nonvolatile memory device | Nov 29, 2006 | Issued |
Array
(
[id] => 38463
[patent_doc_number] => 07788562
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-31
[patent_title] => 'Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data'
[patent_app_type] => utility
[patent_app_number] => 11/606866
[patent_app_country] => US
[patent_app_date] => 2006-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 6508
[patent_no_of_claims] => 29
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/788/07788562.pdf
[firstpage_image] =>[orig_patent_app_number] => 11606866
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/606866 | Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data | Nov 28, 2006 | Issued |
Array
(
[id] => 4831193
[patent_doc_number] => 20080127356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'EMBEDDED SYSTEMS AND METHODS FOR SECURING FIRMWARE THEREIN'
[patent_app_type] => utility
[patent_app_number] => 11/563233
[patent_app_country] => US
[patent_app_date] => 2006-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2271
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[pdf_file] => publications/A1/0127/20080127356.pdf
[firstpage_image] =>[orig_patent_app_number] => 11563233
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/563233 | EMBEDDED SYSTEMS AND METHODS FOR SECURING FIRMWARE THEREIN | Nov 26, 2006 | Abandoned |
Array
(
[id] => 333158
[patent_doc_number] => 07512856
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-31
[patent_title] => 'Register circuit, scanning register circuit utilizing register circuits and scanning method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/562424
[patent_app_country] => US
[patent_app_date] => 2006-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3759
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[pdf_file] => patents/07/512/07512856.pdf
[firstpage_image] =>[orig_patent_app_number] => 11562424
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/562424 | Register circuit, scanning register circuit utilizing register circuits and scanning method thereof | Nov 21, 2006 | Issued |
Array
(
[id] => 261902
[patent_doc_number] => 07574636
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/561023
[patent_app_country] => US
[patent_app_date] => 2006-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 8083
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[pdf_file] => patents/07/574/07574636.pdf
[firstpage_image] =>[orig_patent_app_number] => 11561023
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/561023 | Semiconductor memory device | Nov 16, 2006 | Issued |
Array
(
[id] => 294219
[patent_doc_number] => 07546519
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-09
[patent_title] => 'Method and apparatus for detecting and correcting soft-error upsets in latches'
[patent_app_type] => utility
[patent_app_number] => 11/560420
[patent_app_country] => US
[patent_app_date] => 2006-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3549
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/546/07546519.pdf
[firstpage_image] =>[orig_patent_app_number] => 11560420
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/560420 | Method and apparatus for detecting and correcting soft-error upsets in latches | Nov 15, 2006 | Issued |
Array
(
[id] => 5105635
[patent_doc_number] => 20070064510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Method And Apparatus For Evaluating And Optimizing A Signaling System'
[patent_app_type] => utility
[patent_app_number] => 11/559111
[patent_app_country] => US
[patent_app_date] => 2006-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[firstpage_image] =>[orig_patent_app_number] => 11559111
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559111 | Method and apparatus for evaluating and optimizing a signaling system | Nov 12, 2006 | Issued |
Array
(
[id] => 265588
[patent_doc_number] => 07571362
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-04
[patent_title] => 'Method of managing fails in a non-volatile memory device and relative memory device'
[patent_app_type] => utility
[patent_app_number] => 11/557786
[patent_app_country] => US
[patent_app_date] => 2006-11-08
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[pdf_file] => patents/07/571/07571362.pdf
[firstpage_image] =>[orig_patent_app_number] => 11557786
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/557786 | Method of managing fails in a non-volatile memory device and relative memory device | Nov 7, 2006 | Issued |
Array
(
[id] => 5197899
[patent_doc_number] => 20070297217
[patent_country] => US
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[patent_issue_date] => 2007-12-27
[patent_title] => 'METHOD AND CIRCUIT ARRANGEMENT FOR OPERATING A VOLATILE RANDOM ACCESS MEMORY AS A DETECTOR'
[patent_app_type] => utility
[patent_app_number] => 11/556760
[patent_app_country] => US
[patent_app_date] => 2006-11-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0297/20070297217.pdf
[firstpage_image] =>[orig_patent_app_number] => 11556760
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/556760 | Method and circuit arrangement for operating a volatile random access memory as a detector | Nov 5, 2006 | Issued |
Array
(
[id] => 4592875
[patent_doc_number] => 07853851
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-12-14
[patent_title] => 'Method and apparatus for detecting degradation in an integrated circuit chip'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11593744
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/593744 | Method and apparatus for detecting degradation in an integrated circuit chip | Nov 5, 2006 | Issued |
Array
(
[id] => 171921
[patent_doc_number] => 07669089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'Multi-level file representation corruption'
[patent_app_type] => utility
[patent_app_number] => 11/555614
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11555614
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/555614 | Multi-level file representation corruption | Oct 31, 2006 | Issued |
Array
(
[id] => 106992
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[patent_issue_date] => 2010-06-01
[patent_title] => 'Self test circuit for a semiconductor intergrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/555524 | Self test circuit for a semiconductor intergrated circuit | Oct 31, 2006 | Issued |
Array
(
[id] => 600420
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[patent_title] => 'Testing a multibank memory module'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/555138 | Testing a multibank memory module | Oct 30, 2006 | Issued |
Array
(
[id] => 4966871
[patent_doc_number] => 20080109691
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[patent_issue_date] => 2008-05-08
[patent_title] => 'Method and Apparatus for Executing a BIST Routine'
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[firstpage_image] =>[orig_patent_app_number] => 11553582
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/553582 | Method and Apparatus for Executing a BIST Routine | Oct 26, 2006 | Abandoned |
Array
(
[id] => 5273663
[patent_doc_number] => 20090077439
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[patent_issue_date] => 2009-03-19
[patent_title] => 'INTEGRATED CIRCUIT TEST METHOD AND TEST APPARATUS'
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[firstpage_image] =>[orig_patent_app_number] => 12092186
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/092186 | Integrated circuit test method and test apparatus | Oct 22, 2006 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/582798 | Plesiochronous receiver pin with synchronous mode for testing on ATE | Oct 17, 2006 | Issued |
Array
(
[id] => 860510
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[pdf_file] => patents/07/376/07376885.pdf
[firstpage_image] =>[orig_patent_app_number] => 11582190
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/582190 | Memory efficient LDPC decoding methods and apparatus | Oct 16, 2006 | Issued |