
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 297937
[patent_doc_number] => 07543216
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-06-02
[patent_title] => 'Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture'
[patent_app_type] => utility
[patent_app_number] => 11/550336
[patent_app_country] => US
[patent_app_date] => 2006-10-17
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/543/07543216.pdf
[firstpage_image] =>[orig_patent_app_number] => 11550336
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/550336 | Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture | Oct 16, 2006 | Issued |
Array
(
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[patent_doc_number] => 20080104470
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-01
[patent_title] => 'Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test'
[patent_app_type] => utility
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Array
(
[id] => 4586975
[patent_doc_number] => 07849374
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[patent_issue_date] => 2010-12-07
[patent_title] => 'Testing a transceiver'
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Array
(
[id] => 280024
[patent_doc_number] => 07558997
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[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Wiring structure and method of semiconductor integrated circuit'
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Array
(
[id] => 175655
[patent_doc_number] => 07661038
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[patent_issue_date] => 2010-02-09
[patent_title] => 'Link adaptation for retransmission error-control technique transmissions'
[patent_app_type] => utility
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[patent_app_date] => 2006-10-09
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[pdf_file] => patents/07/661/07661038.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/539867 | Link adaptation for retransmission error-control technique transmissions | Oct 8, 2006 | Issued |
Array
(
[id] => 4684062
[patent_doc_number] => 20080250288
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[patent_issue_date] => 2008-10-09
[patent_title] => 'Scan Testing Methods'
[patent_app_type] => utility
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Array
(
[id] => 5248942
[patent_doc_number] => 20070245176
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[patent_title] => 'BER monitoring circuit'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11502517
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/502517 | BER monitoring circuit | Aug 10, 2006 | Abandoned |
Array
(
[id] => 321455
[patent_doc_number] => 07523369
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[patent_issue_date] => 2009-04-21
[patent_title] => 'Substrate and testing method thereof'
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Array
(
[id] => 4996181
[patent_doc_number] => 20070011526
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[patent_issue_date] => 2007-01-11
[patent_title] => 'Position independent testing of circuits'
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[firstpage_image] =>[orig_patent_app_number] => 11463731
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/463731 | Internal core connected to bond pads by distributor and collector | Aug 9, 2006 | Issued |
Array
(
[id] => 333157
[patent_doc_number] => 07512855
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[patent_issue_date] => 2009-03-31
[patent_title] => 'Shift register circuit'
[patent_app_type] => utility
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Array
(
[id] => 375002
[patent_doc_number] => 07475310
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[patent_issue_date] => 2009-01-06
[patent_title] => 'Signal output circuit, and test apparatus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/501397 | Signal output circuit, and test apparatus | Aug 8, 2006 | Issued |
Array
(
[id] => 358607
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[patent_title] => 'Peripheral connector with boundary-scan test function'
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Array
(
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[patent_title] => 'Methods of testing a user design in a programmable integrated circuit'
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Array
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[id] => 5012719
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[patent_title] => 'Parallel bit test circuits for testing semiconductor memory devices and related methods'
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Array
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Array
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Array
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