Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 297937 [patent_doc_number] => 07543216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-02 [patent_title] => 'Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture' [patent_app_type] => utility [patent_app_number] => 11/550336 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6359 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543216.pdf [firstpage_image] =>[orig_patent_app_number] => 11550336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550336
Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture Oct 16, 2006 Issued
Array ( [id] => 4895370 [patent_doc_number] => 20080104470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test' [patent_app_type] => utility [patent_app_number] => 11/581142 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6432 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104470.pdf [firstpage_image] =>[orig_patent_app_number] => 11581142 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581142
Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test Oct 11, 2006 Issued
Array ( [id] => 4586975 [patent_doc_number] => 07849374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-07 [patent_title] => 'Testing a transceiver' [patent_app_type] => utility [patent_app_number] => 11/546806 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849374.pdf [firstpage_image] =>[orig_patent_app_number] => 11546806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546806
Testing a transceiver Oct 10, 2006 Issued
Array ( [id] => 280024 [patent_doc_number] => 07558997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Wiring structure and method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/544751 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4622 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558997.pdf [firstpage_image] =>[orig_patent_app_number] => 11544751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/544751
Wiring structure and method of semiconductor integrated circuit Oct 9, 2006 Issued
Array ( [id] => 175655 [patent_doc_number] => 07661038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Link adaptation for retransmission error-control technique transmissions' [patent_app_type] => utility [patent_app_number] => 11/539867 [patent_app_country] => US [patent_app_date] => 2006-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8277 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/661/07661038.pdf [firstpage_image] =>[orig_patent_app_number] => 11539867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539867
Link adaptation for retransmission error-control technique transmissions Oct 8, 2006 Issued
Array ( [id] => 4684062 [patent_doc_number] => 20080250288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Scan Testing Methods' [patent_app_type] => utility [patent_app_number] => 12/065935 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3711 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250288.pdf [firstpage_image] =>[orig_patent_app_number] => 12065935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/065935
Scan testing methods Sep 6, 2006 Issued
Array ( [id] => 5248942 [patent_doc_number] => 20070245176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'BER monitoring circuit' [patent_app_type] => utility [patent_app_number] => 11/502517 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245176.pdf [firstpage_image] =>[orig_patent_app_number] => 11502517 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502517
BER monitoring circuit Aug 10, 2006 Abandoned
Array ( [id] => 321455 [patent_doc_number] => 07523369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Substrate and testing method thereof' [patent_app_type] => utility [patent_app_number] => 11/502405 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2309 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523369.pdf [firstpage_image] =>[orig_patent_app_number] => 11502405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/502405
Substrate and testing method thereof Aug 10, 2006 Issued
Array ( [id] => 4996181 [patent_doc_number] => 20070011526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Position independent testing of circuits' [patent_app_type] => utility [patent_app_number] => 11/463731 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 27149 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011526.pdf [firstpage_image] =>[orig_patent_app_number] => 11463731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463731
Internal core connected to bond pads by distributor and collector Aug 9, 2006 Issued
Array ( [id] => 333157 [patent_doc_number] => 07512855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Shift register circuit' [patent_app_type] => utility [patent_app_number] => 11/501796 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4535 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512855.pdf [firstpage_image] =>[orig_patent_app_number] => 11501796 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501796
Shift register circuit Aug 9, 2006 Issued
Array ( [id] => 375002 [patent_doc_number] => 07475310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Signal output circuit, and test apparatus' [patent_app_type] => utility [patent_app_number] => 11/501397 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3242 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475310.pdf [firstpage_image] =>[orig_patent_app_number] => 11501397 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501397
Signal output circuit, and test apparatus Aug 8, 2006 Issued
Array ( [id] => 358607 [patent_doc_number] => 07490277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Peripheral connector with boundary-scan test function' [patent_app_type] => utility [patent_app_number] => 11/500477 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2108 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/490/07490277.pdf [firstpage_image] =>[orig_patent_app_number] => 11500477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500477
Peripheral connector with boundary-scan test function Aug 7, 2006 Issued
Array ( [id] => 571908 [patent_doc_number] => 07469371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-23 [patent_title] => 'Methods of testing a user design in a programmable integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/500526 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3756 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/469/07469371.pdf [firstpage_image] =>[orig_patent_app_number] => 11500526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500526
Methods of testing a user design in a programmable integrated circuit Aug 7, 2006 Issued
Array ( [id] => 5012719 [patent_doc_number] => 20070283198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Parallel bit test circuits for testing semiconductor memory devices and related methods' [patent_app_type] => utility [patent_app_number] => 11/500126 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8708 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283198.pdf [firstpage_image] =>[orig_patent_app_number] => 11500126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500126
Parallel bit test circuits for testing semiconductor memory devices and related methods Aug 6, 2006 Issued
Array ( [id] => 297931 [patent_doc_number] => 07543210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Semiconductor device and test system thereof' [patent_app_type] => utility [patent_app_number] => 11/499661 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7205 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543210.pdf [firstpage_image] =>[orig_patent_app_number] => 11499661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499661
Semiconductor device and test system thereof Aug 6, 2006 Issued
Array ( [id] => 5001355 [patent_doc_number] => 20070043989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Method for specifying failure position in scan chain' [patent_app_type] => utility [patent_app_number] => 11/498757 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5604 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043989.pdf [firstpage_image] =>[orig_patent_app_number] => 11498757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498757
Method for specifying failure position in scan chain Aug 3, 2006 Abandoned
Array ( [id] => 5137571 [patent_doc_number] => 20070079200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Input-output device testing' [patent_app_type] => utility [patent_app_number] => 11/499829 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8743 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079200.pdf [firstpage_image] =>[orig_patent_app_number] => 11499829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499829
Input-output device testing Aug 3, 2006 Issued
Array ( [id] => 5049450 [patent_doc_number] => 20070029994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Semiconductor device and inspection method of semiconductor device and wireless chip' [patent_app_type] => utility [patent_app_number] => 11/494466 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20070029994.pdf [firstpage_image] =>[orig_patent_app_number] => 11494466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/494466
Semiconductor device and inspection method of semiconductor device and wireless chip Jul 27, 2006 Issued
Array ( [id] => 333189 [patent_doc_number] => 07512873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Parallel processing apparatus dynamically switching over circuit configuration' [patent_app_type] => utility [patent_app_number] => 11/494477 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 13977 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512873.pdf [firstpage_image] =>[orig_patent_app_number] => 11494477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/494477
Parallel processing apparatus dynamically switching over circuit configuration Jul 27, 2006 Issued
Array ( [id] => 297929 [patent_doc_number] => 07543208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'JTAG to system bus interface for accessing embedded analysis instruments' [patent_app_type] => utility [patent_app_number] => 11/493784 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543208.pdf [firstpage_image] =>[orig_patent_app_number] => 11493784 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493784
JTAG to system bus interface for accessing embedded analysis instruments Jul 25, 2006 Issued
Menu