Search

David Ton

Examiner (ID: 3564, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2784, 2782, 2138, 2317, 2133
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7591362 [patent_doc_number] => 07653845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Test algorithm selection in memory built-in self test controller' [patent_app_type] => utility [patent_app_number] => 11/484157 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7938 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/653/07653845.pdf [firstpage_image] =>[orig_patent_app_number] => 11484157 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/484157
Test algorithm selection in memory built-in self test controller Jul 10, 2006 Issued
Array ( [id] => 284111 [patent_doc_number] => 07555686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Semiconductor device, test board for testing the same, and test system and method for testing the same' [patent_app_type] => utility [patent_app_number] => 11/483753 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9730 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555686.pdf [firstpage_image] =>[orig_patent_app_number] => 11483753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/483753
Semiconductor device, test board for testing the same, and test system and method for testing the same Jul 9, 2006 Issued
Array ( [id] => 258198 [patent_doc_number] => 07577886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit' [patent_app_type] => utility [patent_app_number] => 11/484355 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3983 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577886.pdf [firstpage_image] =>[orig_patent_app_number] => 11484355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/484355
Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit Jul 9, 2006 Issued
Array ( [id] => 5190520 [patent_doc_number] => 20070168829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Methods to make DRAM fully compatible with SRAM' [patent_app_type] => utility [patent_app_number] => 11/484803 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6675 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168829.pdf [firstpage_image] =>[orig_patent_app_number] => 11484803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/484803
Methods to make DRAM fully compatible with SRAM Jul 9, 2006 Abandoned
Array ( [id] => 317060 [patent_doc_number] => 07526700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/481787 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6860 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526700.pdf [firstpage_image] =>[orig_patent_app_number] => 11481787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/481787
Semiconductor integrated circuit device Jul 6, 2006 Issued
Array ( [id] => 7595724 [patent_doc_number] => 07620858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Fabric-based high speed serial crossbar switch for ATE' [patent_app_type] => utility [patent_app_number] => 11/482589 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4122 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620858.pdf [firstpage_image] =>[orig_patent_app_number] => 11482589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482589
Fabric-based high speed serial crossbar switch for ATE Jul 5, 2006 Issued
Array ( [id] => 5243848 [patent_doc_number] => 20070022343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and computer readable medium for the same' [patent_app_type] => utility [patent_app_number] => 11/480958 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8311 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20070022343.pdf [firstpage_image] =>[orig_patent_app_number] => 11480958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/480958
Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and computer readable medium for the same Jul 5, 2006 Issued
Array ( [id] => 347056 [patent_doc_number] => 07500158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-03 [patent_title] => 'System and method for network device configuration' [patent_app_type] => utility [patent_app_number] => 11/483054 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8762 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/500/07500158.pdf [firstpage_image] =>[orig_patent_app_number] => 11483054 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/483054
System and method for network device configuration Jul 5, 2006 Issued
Array ( [id] => 374992 [patent_doc_number] => 07475300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Test circuit and test method' [patent_app_type] => utility [patent_app_number] => 11/480455 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6730 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475300.pdf [firstpage_image] =>[orig_patent_app_number] => 11480455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/480455
Test circuit and test method Jul 4, 2006 Issued
Array ( [id] => 366712 [patent_doc_number] => 07484136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Signal-to-noise ratio (SNR) determination in the time domain' [patent_app_type] => utility [patent_app_number] => 11/480103 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4949 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484136.pdf [firstpage_image] =>[orig_patent_app_number] => 11480103 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/480103
Signal-to-noise ratio (SNR) determination in the time domain Jun 29, 2006 Issued
Array ( [id] => 362705 [patent_doc_number] => 07487411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Multi symbol bit detection for SDPSK signals' [patent_app_type] => utility [patent_app_number] => 11/478271 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1337 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487411.pdf [firstpage_image] =>[orig_patent_app_number] => 11478271 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478271
Multi symbol bit detection for SDPSK signals Jun 28, 2006 Issued
Array ( [id] => 882380 [patent_doc_number] => 07360131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Printer controller having tamper resistant shadow memory' [patent_app_type] => utility [patent_app_number] => 11/474278 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 14986 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360131.pdf [firstpage_image] =>[orig_patent_app_number] => 11474278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/474278
Printer controller having tamper resistant shadow memory Jun 25, 2006 Issued
Array ( [id] => 4934873 [patent_doc_number] => 20080005648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'DATA COMPRESSION' [patent_app_type] => utility [patent_app_number] => 11/425137 [patent_app_country] => US [patent_app_date] => 2006-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4968 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005648.pdf [firstpage_image] =>[orig_patent_app_number] => 11425137 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/425137
Data compression for use in communication systems Jun 18, 2006 Issued
Array ( [id] => 4996184 [patent_doc_number] => 20070011529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Semiconductor device and test method thereof' [patent_app_type] => utility [patent_app_number] => 11/455158 [patent_app_country] => US [patent_app_date] => 2006-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10487 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011529.pdf [firstpage_image] =>[orig_patent_app_number] => 11455158 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/455158
Semiconductor device and test method thereof Jun 18, 2006 Issued
Array ( [id] => 4592145 [patent_doc_number] => 07836371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'On-chip service processor' [patent_app_type] => utility [patent_app_number] => 11/424610 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 9288 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836371.pdf [firstpage_image] =>[orig_patent_app_number] => 11424610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424610
On-chip service processor Jun 15, 2006 Issued
Array ( [id] => 5015090 [patent_doc_number] => 20070258298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Parallel programming of flash memory during in-circuit test' [patent_app_type] => utility [patent_app_number] => 11/453632 [patent_app_country] => US [patent_app_date] => 2006-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20070258298.pdf [firstpage_image] =>[orig_patent_app_number] => 11453632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/453632
Parallel programming of flash memory during in-circuit test Jun 14, 2006 Abandoned
Array ( [id] => 7689873 [patent_doc_number] => 20070234160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Self test device and self test method for reconfigurable device mounted board' [patent_app_type] => utility [patent_app_number] => 11/451053 [patent_app_country] => US [patent_app_date] => 2006-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234160.pdf [firstpage_image] =>[orig_patent_app_number] => 11451053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451053
Self test device and self test method for reconfigurable device mounted board Jun 11, 2006 Issued
Array ( [id] => 375006 [patent_doc_number] => 07475314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Mechanism for read-only memory built-in self-test' [patent_app_type] => utility [patent_app_number] => 11/450722 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475314.pdf [firstpage_image] =>[orig_patent_app_number] => 11450722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450722
Mechanism for read-only memory built-in self-test Jun 7, 2006 Issued
Array ( [id] => 5167229 [patent_doc_number] => 20070288818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'IC functional and delay fault testing' [patent_app_type] => utility [patent_app_number] => 11/450941 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8710 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288818.pdf [firstpage_image] =>[orig_patent_app_number] => 11450941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450941
IC functional and delay fault testing Jun 7, 2006 Issued
Array ( [id] => 868983 [patent_doc_number] => 07370253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Apparatus and method for high-speed SAS link protocol testing' [patent_app_type] => utility [patent_app_number] => 11/448328 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1223 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/370/07370253.pdf [firstpage_image] =>[orig_patent_app_number] => 11448328 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448328
Apparatus and method for high-speed SAS link protocol testing Jun 6, 2006 Issued
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