
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7689873
[patent_doc_number] => 20070234160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'Self test device and self test method for reconfigurable device mounted board'
[patent_app_type] => utility
[patent_app_number] => 11/451053
[patent_app_country] => US
[patent_app_date] => 2006-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
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[pdf_file] => publications/A1/0234/20070234160.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451053 | Self test device and self test method for reconfigurable device mounted board | Jun 11, 2006 | Issued |
Array
(
[id] => 5167229
[patent_doc_number] => 20070288818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-13
[patent_title] => 'IC functional and delay fault testing'
[patent_app_type] => utility
[patent_app_number] => 11/450941
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[patent_app_date] => 2006-06-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/450941 | IC functional and delay fault testing | Jun 7, 2006 | Issued |
Array
(
[id] => 375006
[patent_doc_number] => 07475314
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[patent_kind] => B2
[patent_issue_date] => 2009-01-06
[patent_title] => 'Mechanism for read-only memory built-in self-test'
[patent_app_type] => utility
[patent_app_number] => 11/450722
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[patent_app_date] => 2006-06-08
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[pdf_file] => patents/07/475/07475314.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/450722 | Mechanism for read-only memory built-in self-test | Jun 7, 2006 | Issued |
Array
(
[id] => 868983
[patent_doc_number] => 07370253
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[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Apparatus and method for high-speed SAS link protocol testing'
[patent_app_type] => utility
[patent_app_number] => 11/448328
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[patent_app_date] => 2006-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/07/370/07370253.pdf
[firstpage_image] =>[orig_patent_app_number] => 11448328
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/448328 | Apparatus and method for high-speed SAS link protocol testing | Jun 6, 2006 | Issued |
Array
(
[id] => 4996198
[patent_doc_number] => 20070011543
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[patent_issue_date] => 2007-01-11
[patent_title] => 'Test pattern generation method'
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[firstpage_image] =>[orig_patent_app_number] => 11447302
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/447302 | Test pattern generation method | Jun 5, 2006 | Abandoned |
Array
(
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[patent_doc_number] => 20070168790
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[patent_issue_date] => 2007-07-19
[patent_title] => 'Apparatus and method for reducing test resources in testing drams'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/445944 | Apparatus and method for reducing test resources in testing drams | Jun 1, 2006 | Abandoned |
Array
(
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[patent_doc_number] => 20070300117
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[patent_title] => 'Mapping logic for loading control of crossbar multiplexer select RAM'
[patent_app_type] => utility
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[patent_app_date] => 2006-05-31
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Array
(
[id] => 5609811
[patent_doc_number] => 20060271327
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[patent_issue_date] => 2006-11-30
[patent_title] => 'SYSTEMS AND METHODS FOR MANAGING MULTI-DEVICE TEST SESSIONS'
[patent_app_type] => utility
[patent_app_number] => 11/421476
[patent_app_country] => US
[patent_app_date] => 2006-05-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421476 | Systems and methods for managing multi-device test sessions | May 30, 2006 | Issued |
Array
(
[id] => 5012718
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[patent_title] => 'Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer'
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Array
(
[id] => 605058
[patent_doc_number] => 07434121
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[patent_issue_date] => 2008-10-07
[patent_title] => 'Integrated memory device and method for its testing and manufacture'
[patent_app_type] => utility
[patent_app_number] => 11/443493
[patent_app_country] => US
[patent_app_date] => 2006-05-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/443493 | Integrated memory device and method for its testing and manufacture | May 29, 2006 | Issued |
Array
(
[id] => 5086971
[patent_doc_number] => 20070277022
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[patent_kind] => A1
[patent_issue_date] => 2007-11-29
[patent_title] => 'METHOD, SYSTEM AND PROGRAM PRODUCT FOR ESTABLISHING DECIMAL FLOATING POINT OPERANDS FOR FACILITATING TESTING OF DECIMAL FLOATING POINT INSTRUCTIONS'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11420045
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420045 | Method, system and program product for establishing decimal floating point operands for facilitating testing of decimal floating point instructions | May 23, 2006 | Issued |
Array
(
[id] => 237750
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/434296 | Method and system for data replication | May 14, 2006 | Issued |
Array
(
[id] => 37740
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Array
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Array
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Array
(
[id] => 5036683
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Array
(
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Array
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Array
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Array
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