Search

David Ton

Examiner (ID: 3564, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2784, 2782, 2138, 2317, 2133
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 404305 [patent_doc_number] => 07293213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-06 [patent_title] => 'Method for detecting software errors and vulnerabilities' [patent_app_type] => utility [patent_app_number] => 11/214420 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3108 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/293/07293213.pdf [firstpage_image] =>[orig_patent_app_number] => 11214420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214420
Method for detecting software errors and vulnerabilities Aug 28, 2005 Issued
Array ( [id] => 600430 [patent_doc_number] => 07437640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Fault diagnosis of compressed test responses having one or more unknown states' [patent_app_type] => utility [patent_app_number] => 11/213672 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 28844 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437640.pdf [firstpage_image] =>[orig_patent_app_number] => 11213672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213672
Fault diagnosis of compressed test responses having one or more unknown states Aug 24, 2005 Issued
Array ( [id] => 393005 [patent_doc_number] => 07302624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Adaptive fault diagnosis of compressed test responses' [patent_app_type] => utility [patent_app_number] => 11/213327 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 28849 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302624.pdf [firstpage_image] =>[orig_patent_app_number] => 11213327 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213327
Adaptive fault diagnosis of compressed test responses Aug 24, 2005 Issued
Array ( [id] => 5836558 [patent_doc_number] => 20060248390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Test program debugger device, semiconductor test apparatus, test program debugging method and test method' [patent_app_type] => utility [patent_app_number] => 11/211162 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4794 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20060248390.pdf [firstpage_image] =>[orig_patent_app_number] => 11211162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211162
Test program debugger device, semiconductor test apparatus, test program debugging method and test method Aug 23, 2005 Issued
Array ( [id] => 5882643 [patent_doc_number] => 20060031726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays' [patent_app_type] => utility [patent_app_number] => 11/197989 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4948 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20060031726.pdf [firstpage_image] =>[orig_patent_app_number] => 11197989 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197989
Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays Aug 4, 2005 Issued
Array ( [id] => 411508 [patent_doc_number] => 07287203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Testing embedded RAM blocks by employing RAM scan techniques' [patent_app_type] => utility [patent_app_number] => 11/194540 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3659 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287203.pdf [firstpage_image] =>[orig_patent_app_number] => 11194540 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194540
Testing embedded RAM blocks by employing RAM scan techniques Aug 1, 2005 Issued
Array ( [id] => 372089 [patent_doc_number] => 07478288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Method and apparatus for recording data on and reproducing data from a recording medium and the recording medium' [patent_app_type] => utility [patent_app_number] => 11/193532 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5529 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/478/07478288.pdf [firstpage_image] =>[orig_patent_app_number] => 11193532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/193532
Method and apparatus for recording data on and reproducing data from a recording medium and the recording medium Jul 31, 2005 Issued
Array ( [id] => 5795112 [patent_doc_number] => 20060015793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method of combining multilevel memory cells for an error correction scheme' [patent_app_type] => utility [patent_app_number] => 11/183601 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1796 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015793.pdf [firstpage_image] =>[orig_patent_app_number] => 11183601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183601
Method of combining multilevel memory cells for an error correction scheme Jul 17, 2005 Issued
Array ( [id] => 5052914 [patent_doc_number] => 20070033459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Method for enabling scan of defective ram prior to repair' [patent_app_type] => utility [patent_app_number] => 11/180416 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2481 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20070033459.pdf [firstpage_image] =>[orig_patent_app_number] => 11180416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180416
Method for enabling scan of defective ram prior to repair Jul 12, 2005 Issued
Array ( [id] => 5592346 [patent_doc_number] => 20060041799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Test apparatus, phase adjusting method and memory controller' [patent_app_type] => utility [patent_app_number] => 11/180895 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8657 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20060041799.pdf [firstpage_image] =>[orig_patent_app_number] => 11180895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180895
Test apparatus, phase adjusting method and memory controller Jul 12, 2005 Issued
Array ( [id] => 4996183 [patent_doc_number] => 20070011528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Method and apparatus for testing an ultrasound system' [patent_app_type] => utility [patent_app_number] => 11/154442 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011528.pdf [firstpage_image] =>[orig_patent_app_number] => 11154442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/154442
Method and apparatus for testing an ultrasound system Jun 15, 2005 Issued
Array ( [id] => 4996193 [patent_doc_number] => 20070011538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'CIRCUIT AND METHOD FOR PERFORMING BUILT-IN SELF TEST AND COMPUTER READABLE RECORDING MEDIUM FOR STORING PROGRAM THEREOF' [patent_app_type] => utility [patent_app_number] => 11/160102 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2718 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011538.pdf [firstpage_image] =>[orig_patent_app_number] => 11160102 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160102
Circuit and method for performing built-in self test and computer readable recording medium for storing program thereof Jun 8, 2005 Issued
Array ( [id] => 5734697 [patent_doc_number] => 20060259814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Method and system for optimizing testing of memory stores' [patent_app_type] => utility [patent_app_number] => 11/127590 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259814.pdf [firstpage_image] =>[orig_patent_app_number] => 11127590 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127590
Method and system for optimizing testing of memory stores May 11, 2005 Issued
Array ( [id] => 5663150 [patent_doc_number] => 20060253746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Phase adjust using relative error' [patent_app_type] => utility [patent_app_number] => 11/123355 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8292 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253746.pdf [firstpage_image] =>[orig_patent_app_number] => 11123355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/123355
Phase adjust using relative error May 3, 2005 Issued
Array ( [id] => 5836579 [patent_doc_number] => 20060248411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Methods and apparatus for reducing memory errors' [patent_app_type] => utility [patent_app_number] => 11/116625 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20060248411.pdf [firstpage_image] =>[orig_patent_app_number] => 11116625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/116625
Methods and apparatus for reducing memory errors Apr 27, 2005 Issued
Array ( [id] => 5919552 [patent_doc_number] => 20060239088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'METHOD AND APPARATUS FOR INCREASING FUSE PROGRAMMING YIELD THROUGH PREFERRED USE OF DUPLICATE DATA' [patent_app_type] => utility [patent_app_number] => 10/908033 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8160 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20060239088.pdf [firstpage_image] =>[orig_patent_app_number] => 10908033 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908033
Method and apparatus for increasing fuse programming yield through preferred use of duplicate data Apr 25, 2005 Issued
Array ( [id] => 6932660 [patent_doc_number] => 20050283695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/101377 [patent_app_country] => US [patent_app_date] => 2005-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5161 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20050283695.pdf [firstpage_image] =>[orig_patent_app_number] => 11101377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/101377
Integrated circuit Apr 6, 2005 Issued
Array ( [id] => 411507 [patent_doc_number] => 07287202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Method and apparatus for testing a memory interface' [patent_app_type] => utility [patent_app_number] => 11/100031 [patent_app_country] => US [patent_app_date] => 2005-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10109 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287202.pdf [firstpage_image] =>[orig_patent_app_number] => 11100031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/100031
Method and apparatus for testing a memory interface Apr 4, 2005 Issued
Array ( [id] => 5663165 [patent_doc_number] => 20060253761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Method of making tissue simulating analog materials and models made from same' [patent_app_type] => utility [patent_app_number] => 11/098248 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8521 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253761.pdf [firstpage_image] =>[orig_patent_app_number] => 11098248 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098248
Method of making tissue simulating analog materials and models made from same Apr 3, 2005 Issued
Array ( [id] => 525224 [patent_doc_number] => 07197679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method for testing an integrated semiconductor memory with a shortened reading time' [patent_app_type] => utility [patent_app_number] => 11/095670 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6598 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197679.pdf [firstpage_image] =>[orig_patent_app_number] => 11095670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095670
Method for testing an integrated semiconductor memory with a shortened reading time Mar 31, 2005 Issued
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