
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6932660
[patent_doc_number] => 20050283695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/101377
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5161
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0283/20050283695.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101377
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101377 | Integrated circuit | Apr 6, 2005 | Issued |
Array
(
[id] => 411507
[patent_doc_number] => 07287202
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-23
[patent_title] => 'Method and apparatus for testing a memory interface'
[patent_app_type] => utility
[patent_app_number] => 11/100031
[patent_app_country] => US
[patent_app_date] => 2005-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 10109
[patent_no_of_claims] => 62
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/287/07287202.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100031
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100031 | Method and apparatus for testing a memory interface | Apr 4, 2005 | Issued |
Array
(
[id] => 5663165
[patent_doc_number] => 20060253761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'Method of making tissue simulating analog materials and models made from same'
[patent_app_type] => utility
[patent_app_number] => 11/098248
[patent_app_country] => US
[patent_app_date] => 2005-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8521
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20060253761.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098248
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098248 | Method of making tissue simulating analog materials and models made from same | Apr 3, 2005 | Issued |
Array
(
[id] => 525224
[patent_doc_number] => 07197679
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Method for testing an integrated semiconductor memory with a shortened reading time'
[patent_app_type] => utility
[patent_app_number] => 11/095670
[patent_app_country] => US
[patent_app_date] => 2005-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 6598
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/197/07197679.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095670
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095670 | Method for testing an integrated semiconductor memory with a shortened reading time | Mar 31, 2005 | Issued |
Array
(
[id] => 5852990
[patent_doc_number] => 20060236181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'Systems and methods for LBIST testing using multiple functional subphases'
[patent_app_type] => utility
[patent_app_number] => 11/096787
[patent_app_country] => US
[patent_app_date] => 2005-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8871
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0236/20060236181.pdf
[firstpage_image] =>[orig_patent_app_number] => 11096787
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/096787 | Systems and methods for LBIST testing using multiple functional subphases | Mar 31, 2005 | Issued |
Array
(
[id] => 5928173
[patent_doc_number] => 20060242525
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-26
[patent_title] => 'Method and apparatus for functionally verifying a physical device under test'
[patent_app_type] => utility
[patent_app_number] => 11/095226
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4074
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20060242525.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095226
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095226 | Method and apparatus for functionally verifying a physical device under test | Mar 30, 2005 | Issued |
Array
(
[id] => 5852985
[patent_doc_number] => 20060236176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/097936
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6479
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0236/20060236176.pdf
[firstpage_image] =>[orig_patent_app_number] => 11097936
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/097936 | Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits | Mar 30, 2005 | Issued |
Array
(
[id] => 393013
[patent_doc_number] => 07302627
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-11-27
[patent_title] => 'Apparatus for efficient LFSR calculation in a SIMD processor'
[patent_app_type] => utility
[patent_app_number] => 11/095435
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5280
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/302/07302627.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095435
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095435 | Apparatus for efficient LFSR calculation in a SIMD processor | Mar 30, 2005 | Issued |
Array
(
[id] => 462577
[patent_doc_number] => 07246292
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Apparatus and method for bit pattern learning and computer product'
[patent_app_type] => utility
[patent_app_number] => 11/093244
[patent_app_country] => US
[patent_app_date] => 2005-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6292
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/246/07246292.pdf
[firstpage_image] =>[orig_patent_app_number] => 11093244
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/093244 | Apparatus and method for bit pattern learning and computer product | Mar 29, 2005 | Issued |
Array
(
[id] => 7601885
[patent_doc_number] => 07237161
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'Remote integrated circuit testing method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/094455
[patent_app_country] => US
[patent_app_date] => 2005-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6950
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/237/07237161.pdf
[firstpage_image] =>[orig_patent_app_number] => 11094455
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/094455 | Remote integrated circuit testing method and apparatus | Mar 29, 2005 | Issued |
Array
(
[id] => 407317
[patent_doc_number] => 07290189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-30
[patent_title] => 'Compilation of calibration information for plural testflows'
[patent_app_type] => utility
[patent_app_number] => 11/091681
[patent_app_country] => US
[patent_app_date] => 2005-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1248
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/290/07290189.pdf
[firstpage_image] =>[orig_patent_app_number] => 11091681
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/091681 | Compilation of calibration information for plural testflows | Mar 27, 2005 | Issued |
Array
(
[id] => 388755
[patent_doc_number] => 07305598
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-12-04
[patent_title] => 'Test clock generation for higher-speed testing of a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/089994
[patent_app_country] => US
[patent_app_date] => 2005-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4232
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/305/07305598.pdf
[firstpage_image] =>[orig_patent_app_number] => 11089994
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/089994 | Test clock generation for higher-speed testing of a semiconductor device | Mar 24, 2005 | Issued |
Array
(
[id] => 5615305
[patent_doc_number] => 20060117234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'Programmable logic device, information processing device and programmable logic device control method'
[patent_app_type] => utility
[patent_app_number] => 11/089141
[patent_app_country] => US
[patent_app_date] => 2005-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6015
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20060117234.pdf
[firstpage_image] =>[orig_patent_app_number] => 11089141
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/089141 | Programmable logic device, information processing device and programmable logic device control method | Mar 24, 2005 | Issued |
Array
(
[id] => 481611
[patent_doc_number] => 07228473
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Integrated module having a plurality of separate substrates'
[patent_app_type] => utility
[patent_app_number] => 11/090831
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3395
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/228/07228473.pdf
[firstpage_image] =>[orig_patent_app_number] => 11090831
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/090831 | Integrated module having a plurality of separate substrates | Mar 23, 2005 | Issued |
Array
(
[id] => 513677
[patent_doc_number] => 07206984
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Built-in self test circuit and test method for storage device'
[patent_app_type] => utility
[patent_app_number] => 11/089232
[patent_app_country] => US
[patent_app_date] => 2005-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7202
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/206/07206984.pdf
[firstpage_image] =>[orig_patent_app_number] => 11089232
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/089232 | Built-in self test circuit and test method for storage device | Mar 22, 2005 | Issued |
Array
(
[id] => 6953959
[patent_doc_number] => 20050229054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/086655
[patent_app_country] => US
[patent_app_date] => 2005-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6355
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20050229054.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086655
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086655 | Integrated circuit | Mar 22, 2005 | Issued |
Array
(
[id] => 832675
[patent_doc_number] => 07401274
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-15
[patent_title] => 'Method of performing programming and diagnostic functions for a microcontroller'
[patent_app_type] => utility
[patent_app_number] => 11/086539
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2583
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/401/07401274.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086539
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086539 | Method of performing programming and diagnostic functions for a microcontroller | Mar 21, 2005 | Issued |
Array
(
[id] => 6962628
[patent_doc_number] => 20050216809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Memory module with parallel testing'
[patent_app_type] => utility
[patent_app_number] => 11/086059
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4879
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20050216809.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086059
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086059 | Memory module with parallel testing | Mar 21, 2005 | Issued |
Array
(
[id] => 414906
[patent_doc_number] => 07284171
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'Integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 11/085149
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 5203
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/284/07284171.pdf
[firstpage_image] =>[orig_patent_app_number] => 11085149
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/085149 | Integrated circuit device | Mar 21, 2005 | Issued |
Array
(
[id] => 469587
[patent_doc_number] => 07240255
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Area efficient BIST system for memories'
[patent_app_type] => utility
[patent_app_number] => 11/088636
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3130
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/240/07240255.pdf
[firstpage_image] =>[orig_patent_app_number] => 11088636
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/088636 | Area efficient BIST system for memories | Mar 21, 2005 | Issued |