Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 379127 [patent_doc_number] => 07313740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Internally generating patterns for testing in an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/083473 [patent_app_country] => US [patent_app_date] => 2005-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 10565 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313740.pdf [firstpage_image] =>[orig_patent_app_number] => 11083473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/083473
Internally generating patterns for testing in an integrated circuit device Mar 17, 2005 Issued
Array ( [id] => 540268 [patent_doc_number] => 07188289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Test circuit and circuit test method' [patent_app_type] => utility [patent_app_number] => 11/081619 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4173 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/188/07188289.pdf [firstpage_image] =>[orig_patent_app_number] => 11081619 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/081619
Test circuit and circuit test method Mar 16, 2005 Issued
Array ( [id] => 7178184 [patent_doc_number] => 20050204222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Apparatus and method for eliminating the TMS connection in a JTAG procedure' [patent_app_type] => utility [patent_app_number] => 11/080701 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1918 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204222.pdf [firstpage_image] =>[orig_patent_app_number] => 11080701 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080701
Apparatus and method for eliminating the TMS connection in a JTAG procedure Mar 14, 2005 Abandoned
Array ( [id] => 7178217 [patent_doc_number] => 20050204234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Method and apparatus for the memory self-test of embedded memories in semiconductor chips' [patent_app_type] => utility [patent_app_number] => 11/078668 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204234.pdf [firstpage_image] =>[orig_patent_app_number] => 11078668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078668
Method and apparatus for the memory self-test of embedded memories in semiconductor chips Mar 10, 2005 Issued
Array ( [id] => 599420 [patent_doc_number] => 07444569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Semiconductor integrated circuit having test circuitry with reduced power consumption' [patent_app_type] => utility [patent_app_number] => 11/074735 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4644 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444569.pdf [firstpage_image] =>[orig_patent_app_number] => 11074735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/074735
Semiconductor integrated circuit having test circuitry with reduced power consumption Mar 8, 2005 Issued
Array ( [id] => 549892 [patent_doc_number] => 07185252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Measurement circuit and method for serially merging single-ended signals to analyze them' [patent_app_type] => utility [patent_app_number] => 11/075790 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185252.pdf [firstpage_image] =>[orig_patent_app_number] => 11075790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/075790
Measurement circuit and method for serially merging single-ended signals to analyze them Mar 7, 2005 Issued
Array ( [id] => 7109090 [patent_doc_number] => 20050206544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Digital-to-analog conversion with an interleaved, pulse-width modulated signal' [patent_app_type] => utility [patent_app_number] => 11/073682 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4527 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20050206544.pdf [firstpage_image] =>[orig_patent_app_number] => 11073682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/073682
Digital-to-analog conversion with an interleaved, pulse-width modulated signal Mar 7, 2005 Issued
Array ( [id] => 5684440 [patent_doc_number] => 20060200710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Bit error rate performance estimation and control' [patent_app_type] => utility [patent_app_number] => 11/072861 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200710.pdf [firstpage_image] =>[orig_patent_app_number] => 11072861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/072861
Bit error rate performance estimation and control Mar 3, 2005 Abandoned
Array ( [id] => 478556 [patent_doc_number] => 07231569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Scan flip-flop circuit with reduced power consumption' [patent_app_type] => utility [patent_app_number] => 11/068908 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4065 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231569.pdf [firstpage_image] =>[orig_patent_app_number] => 11068908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068908
Scan flip-flop circuit with reduced power consumption Mar 1, 2005 Issued
Array ( [id] => 7073741 [patent_doc_number] => 20050147008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method for creating defect management information in an recording medium, and apparatus and medium based on said method' [patent_app_type] => utility [patent_app_number] => 11/068866 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5366 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20050147008.pdf [firstpage_image] =>[orig_patent_app_number] => 11068866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068866
Method for creating defect management information in an recording medium, and apparatus and medium based on said method Mar 1, 2005 Issued
Array ( [id] => 846281 [patent_doc_number] => 07389451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Memory redundancy with programmable control' [patent_app_type] => utility [patent_app_number] => 11/067356 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389451.pdf [firstpage_image] =>[orig_patent_app_number] => 11067356 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067356
Memory redundancy with programmable control Feb 24, 2005 Issued
Array ( [id] => 7245545 [patent_doc_number] => 20050141303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Look-up table for use with redundant memory' [patent_app_type] => utility [patent_app_number] => 11/067326 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141303.pdf [firstpage_image] =>[orig_patent_app_number] => 11067326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067326
Look-up table for use with redundant memory Feb 24, 2005 Issued
Array ( [id] => 945882 [patent_doc_number] => 06968482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Memory redundancy with programmable non-volatile control' [patent_app_type] => utility [patent_app_number] => 11/067355 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968482.pdf [firstpage_image] =>[orig_patent_app_number] => 11067355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067355
Memory redundancy with programmable non-volatile control Feb 24, 2005 Issued
Array ( [id] => 5621243 [patent_doc_number] => 20060190778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method for reducing SRAM test time by applying power-up state knowledge' [patent_app_type] => utility [patent_app_number] => 11/063922 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190778.pdf [firstpage_image] =>[orig_patent_app_number] => 11063922 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063922
Method for reducing SRAM test time by applying power-up state knowledge Feb 22, 2005 Issued
Array ( [id] => 5621242 [patent_doc_number] => 20060190777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Memory command unit throttle and error recovery' [patent_app_type] => utility [patent_app_number] => 11/060496 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5183 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190777.pdf [firstpage_image] =>[orig_patent_app_number] => 11060496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060496
Memory command unit throttle and error recovery Feb 17, 2005 Issued
Array ( [id] => 4690153 [patent_doc_number] => 20080034334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Integrated Circuit Chip with Communication Means Enabling Remote Control of Testing Means of Ip Cores of the Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 10/589489 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7684 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034334.pdf [firstpage_image] =>[orig_patent_app_number] => 10589489 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/589489
Integrated circuit chip with communication means enabling remote control of testing means of IP cores of the integrated circuit Feb 16, 2005 Issued
Array ( [id] => 829296 [patent_doc_number] => 07404114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'System and method for balancing delay of signal communication paths through well voltage adjustment' [patent_app_type] => utility [patent_app_number] => 10/906343 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3647 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404114.pdf [firstpage_image] =>[orig_patent_app_number] => 10906343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906343
System and method for balancing delay of signal communication paths through well voltage adjustment Feb 14, 2005 Issued
Array ( [id] => 7178156 [patent_doc_number] => 20050204212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Data memory system' [patent_app_type] => utility [patent_app_number] => 11/055782 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 29009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204212.pdf [firstpage_image] =>[orig_patent_app_number] => 11055782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055782
Data memory system Feb 10, 2005 Issued
Array ( [id] => 5674014 [patent_doc_number] => 20060179369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability' [patent_app_type] => utility [patent_app_number] => 11/055195 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4320 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179369.pdf [firstpage_image] =>[orig_patent_app_number] => 11055195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055195
Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability Feb 9, 2005 Issued
Array ( [id] => 829315 [patent_doc_number] => 07404125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Compilable memory structure and test methodology for both ASIC and foundry test environments' [patent_app_type] => utility [patent_app_number] => 10/906147 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3286 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404125.pdf [firstpage_image] =>[orig_patent_app_number] => 10906147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906147
Compilable memory structure and test methodology for both ASIC and foundry test environments Feb 3, 2005 Issued
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