David Ton

Array ( [id] => 599420 [patent_doc_number] => 07444569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Semiconductor integrated circuit having test circuitry with reduced power consumption' [patent_app_type] => utility [patent_app_number] => 11/074735 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4644 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444569.pdf [firstpage_image] =>[orig_patent_app_number] => 11074735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7109090 [patent_doc_number] => 20050206544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Digital-to-analog conversion with an interleaved, pulse-width modulated signal' [patent_app_type] => utility [patent_app_number] => 11/073682 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4527 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20050206544.pdf [firstpage_image] =>[orig_patent_app_number] => 11073682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 549892 [patent_doc_number] => 07185252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Measurement circuit and method for serially merging single-ended signals to analyze them' [patent_app_type] => utility [patent_app_number] => 11/075790 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185252.pdf [firstpage_image] =>[orig_patent_app_number] => 11075790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5684440 [patent_doc_number] => 20060200710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Bit error rate performance estimation and control' [patent_app_type] => utility [patent_app_number] => 11/072861 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200710.pdf [firstpage_image] =>[orig_patent_app_number] => 11072861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 478556 [patent_doc_number] => 07231569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Scan flip-flop circuit with reduced power consumption' [patent_app_type] => utility [patent_app_number] => 11/068908 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4065 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231569.pdf [firstpage_image] =>[orig_patent_app_number] => 11068908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7073741 [patent_doc_number] => 20050147008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method for creating defect management information in an recording medium, and apparatus and medium based on said method' [patent_app_type] => utility [patent_app_number] => 11/068866 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5366 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20050147008.pdf [firstpage_image] =>[orig_patent_app_number] => 11068866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7245545 [patent_doc_number] => 20050141303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Look-up table for use with redundant memory' [patent_app_type] => utility [patent_app_number] => 11/067326 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141303.pdf [firstpage_image] =>[orig_patent_app_number] => 11067326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 945882 [patent_doc_number] => 06968482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Memory redundancy with programmable non-volatile control' [patent_app_type] => utility [patent_app_number] => 11/067355 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968482.pdf [firstpage_image] =>[orig_patent_app_number] => 11067355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 846281 [patent_doc_number] => 07389451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Memory redundancy with programmable control' [patent_app_type] => utility [patent_app_number] => 11/067356 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389451.pdf [firstpage_image] =>[orig_patent_app_number] => 11067356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5621243 [patent_doc_number] => 20060190778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method for reducing SRAM test time by applying power-up state knowledge' [patent_app_type] => utility [patent_app_number] => 11/063922 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190778.pdf [firstpage_image] =>[orig_patent_app_number] => 11063922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5621242 [patent_doc_number] => 20060190777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Memory command unit throttle and error recovery' [patent_app_type] => utility [patent_app_number] => 11/060496 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5183 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190777.pdf [firstpage_image] =>[orig_patent_app_number] => 11060496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4690153 [patent_doc_number] => 20080034334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Integrated Circuit Chip with Communication Means Enabling Remote Control of Testing Means of Ip Cores of the Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 10/589489 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7684 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034334.pdf [firstpage_image] =>[orig_patent_app_number] => 10589489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 829296 [patent_doc_number] => 07404114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'System and method for balancing delay of signal communication paths through well voltage adjustment' [patent_app_type] => utility [patent_app_number] => 10/906343 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3647 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404114.pdf [firstpage_image] =>[orig_patent_app_number] => 10906343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7178156 [patent_doc_number] => 20050204212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Data memory system' [patent_app_type] => utility [patent_app_number] => 11/055782 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 29009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204212.pdf [firstpage_image] =>[orig_patent_app_number] => 11055782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5674014 [patent_doc_number] => 20060179369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability' [patent_app_type] => utility [patent_app_number] => 11/055195 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4320 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179369.pdf [firstpage_image] =>[orig_patent_app_number] => 11055195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 829315 [patent_doc_number] => 07404125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Compilable memory structure and test methodology for both ASIC and foundry test environments' [patent_app_type] => utility [patent_app_number] => 10/906147 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3286 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404125.pdf [firstpage_image] =>[orig_patent_app_number] => 10906147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5774345 [patent_doc_number] => 20050268199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Method and circuit for reducing SATA transmission data errors by adjusting the period of sending ALIGN primitives' [patent_app_type] => utility [patent_app_number] => 11/039923 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2469 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268199.pdf [firstpage_image] =>[orig_patent_app_number] => 11039923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 605084 [patent_doc_number] => 07434132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Method and system of configuring a software program' [patent_app_type] => utility [patent_app_number] => 11/036106 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5079 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434132.pdf [firstpage_image] =>[orig_patent_app_number] => 11036106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7006882 [patent_doc_number] => 20050172195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Errored bit sequence identifying method and decision feedback equalizer' [patent_app_type] => utility [patent_app_number] => 11/034809 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5051 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172195.pdf [firstpage_image] =>[orig_patent_app_number] => 11034809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 843724 [patent_doc_number] => 07392441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Method of performing operational validation with limited CPU use of a communications network' [patent_app_type] => utility [patent_app_number] => 11/032179 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2295 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/392/07392441.pdf [firstpage_image] =>[orig_patent_app_number] => 11032179 [rel_patent_id] =>[rel_patent_doc_number] =>)