Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5774345 [patent_doc_number] => 20050268199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Method and circuit for reducing SATA transmission data errors by adjusting the period of sending ALIGN primitives' [patent_app_type] => utility [patent_app_number] => 11/039923 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2469 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268199.pdf [firstpage_image] =>[orig_patent_app_number] => 11039923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/039923
Method and circuit for reducing SATA transmission data errors by adjusting the period of sending ALIGN primitives Jan 23, 2005 Issued
Array ( [id] => 605084 [patent_doc_number] => 07434132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Method and system of configuring a software program' [patent_app_type] => utility [patent_app_number] => 11/036106 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5079 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434132.pdf [firstpage_image] =>[orig_patent_app_number] => 11036106 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036106
Method and system of configuring a software program Jan 17, 2005 Issued
Array ( [id] => 7006882 [patent_doc_number] => 20050172195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Errored bit sequence identifying method and decision feedback equalizer' [patent_app_type] => utility [patent_app_number] => 11/034809 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5051 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172195.pdf [firstpage_image] =>[orig_patent_app_number] => 11034809 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034809
Errored bit sequence identifying method and decision feedback equalizer Jan 13, 2005 Abandoned
Array ( [id] => 843724 [patent_doc_number] => 07392441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Method of performing operational validation with limited CPU use of a communications network' [patent_app_type] => utility [patent_app_number] => 11/032179 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2295 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/392/07392441.pdf [firstpage_image] =>[orig_patent_app_number] => 11032179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032179
Method of performing operational validation with limited CPU use of a communications network Jan 9, 2005 Issued
Array ( [id] => 208631 [patent_doc_number] => 07631239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Method for retransmitting packet in mobile communication system and computer-readable medium recorded program thereof' [patent_app_type] => utility [patent_app_number] => 10/585052 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7072 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/631/07631239.pdf [firstpage_image] =>[orig_patent_app_number] => 10585052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/585052
Method for retransmitting packet in mobile communication system and computer-readable medium recorded program thereof Dec 28, 2004 Issued
Array ( [id] => 7603524 [patent_doc_number] => 07117416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method and apparatus to facilitate self-testing of a system on chip' [patent_app_type] => utility [patent_app_number] => 11/021636 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6725 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117416.pdf [firstpage_image] =>[orig_patent_app_number] => 11021636 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021636
Method and apparatus to facilitate self-testing of a system on chip Dec 22, 2004 Issued
Array ( [id] => 7006880 [patent_doc_number] => 20050172193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Tap time division multiplexing' [patent_app_type] => utility [patent_app_number] => 11/015330 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13946 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172193.pdf [firstpage_image] =>[orig_patent_app_number] => 11015330 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015330
Tap time division multiplexing Dec 16, 2004 Issued
Array ( [id] => 6927590 [patent_doc_number] => 20050240847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Clock controller for at-speed testing of scan circuits' [patent_app_type] => utility [patent_app_number] => 11/013319 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6432 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240847.pdf [firstpage_image] =>[orig_patent_app_number] => 11013319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013319
Clock controller for at-speed testing of scan circuits Dec 16, 2004 Issued
Array ( [id] => 7207218 [patent_doc_number] => 20050166105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Tap multiplexer' [patent_app_type] => utility [patent_app_number] => 11/015748 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166105.pdf [firstpage_image] =>[orig_patent_app_number] => 11015748 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015748
Tap multiplexer Dec 16, 2004 Issued
Array ( [id] => 5651056 [patent_doc_number] => 20060136791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Test method, control circuit and system for reduced time combined write window and retention testing' [patent_app_type] => utility [patent_app_number] => 11/012322 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2785 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136791.pdf [firstpage_image] =>[orig_patent_app_number] => 11012322 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012322
Test method, control circuit and system for reduced time combined write window and retention testing Dec 15, 2004 Abandoned
Array ( [id] => 438506 [patent_doc_number] => 07263638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Memory having test circuit' [patent_app_type] => utility [patent_app_number] => 11/013870 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5248 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/263/07263638.pdf [firstpage_image] =>[orig_patent_app_number] => 11013870 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013870
Memory having test circuit Dec 15, 2004 Issued
Array ( [id] => 200945 [patent_doc_number] => 07640466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Semiconductor integrated circuit device incorporating a data memory testing circuit' [patent_app_type] => utility [patent_app_number] => 11/012190 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5247 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640466.pdf [firstpage_image] =>[orig_patent_app_number] => 11012190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012190
Semiconductor integrated circuit device incorporating a data memory testing circuit Dec 15, 2004 Issued
Array ( [id] => 5695981 [patent_doc_number] => 20060156128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'System and method for implementing postponed quasi-masking test output compression in integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/013641 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4088 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156128.pdf [firstpage_image] =>[orig_patent_app_number] => 11013641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013641
System and method for implementing postponed quasi-masking test output compression in integrated circuit Dec 15, 2004 Issued
Array ( [id] => 7077355 [patent_doc_number] => 20050149803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/012355 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7151 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149803.pdf [firstpage_image] =>[orig_patent_app_number] => 11012355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012355
Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory Dec 15, 2004 Issued
Array ( [id] => 490544 [patent_doc_number] => 07222282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Embedded micro computer unit (MCU) for high-speed testing using a memory emulation module and a method of testing the same' [patent_app_type] => utility [patent_app_number] => 11/013116 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2064 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222282.pdf [firstpage_image] =>[orig_patent_app_number] => 11013116 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013116
Embedded micro computer unit (MCU) for high-speed testing using a memory emulation module and a method of testing the same Dec 14, 2004 Issued
Array ( [id] => 5916862 [patent_doc_number] => 20060129899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Monitoring of solid state memory devices in active memory system utilizing redundant devices' [patent_app_type] => utility [patent_app_number] => 11/013150 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8673 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129899.pdf [firstpage_image] =>[orig_patent_app_number] => 11013150 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013150
Monitoring of solid state memory devices in active memory system utilizing redundant devices Dec 14, 2004 Issued
Array ( [id] => 5909788 [patent_doc_number] => 20060125506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'RFID tag with bist circuits' [patent_app_type] => utility [patent_app_number] => 11/014076 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9032 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20060125506.pdf [firstpage_image] =>[orig_patent_app_number] => 11014076 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/014076
RFID tag with bist circuits Dec 14, 2004 Issued
Array ( [id] => 5197298 [patent_doc_number] => 20070296616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Signal Transmitting and Receiving Device and Method of Mobile Communication System' [patent_app_type] => utility [patent_app_number] => 11/660152 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4129 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20070296616.pdf [firstpage_image] =>[orig_patent_app_number] => 11660152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/660152
Signal transmitting and receiving device and method of mobile communication system Nov 9, 2004 Issued
Array ( [id] => 877804 [patent_doc_number] => 07363568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'System and method for testing differential signal crossover using undersampling' [patent_app_type] => utility [patent_app_number] => 10/979981 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 9411 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363568.pdf [firstpage_image] =>[orig_patent_app_number] => 10979981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979981
System and method for testing differential signal crossover using undersampling Nov 2, 2004 Issued
Array ( [id] => 7548615 [patent_doc_number] => RE042963 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-11-22 [patent_title] => 'Turbo interleaving apparatus and method' [patent_app_type] => reissue [patent_app_number] => 10/973100 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12018 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/042/RE042963.pdf [firstpage_image] =>[orig_patent_app_number] => 10973100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973100
Turbo interleaving apparatus and method Oct 24, 2004 Issued
Menu