
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7548615
[patent_doc_number] => RE042963
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2011-11-22
[patent_title] => 'Turbo interleaving apparatus and method'
[patent_app_type] => reissue
[patent_app_number] => 10/973100
[patent_app_country] => US
[patent_app_date] => 2004-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 12018
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/042/RE042963.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973100
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973100 | Turbo interleaving apparatus and method | Oct 24, 2004 | Issued |
Array
(
[id] => 7548615
[patent_doc_number] => RE042963
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2011-11-22
[patent_title] => 'Turbo interleaving apparatus and method'
[patent_app_type] => reissue
[patent_app_number] => 10/973100
[patent_app_country] => US
[patent_app_date] => 2004-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 12018
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/042/RE042963.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973100
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973100 | Turbo interleaving apparatus and method | Oct 24, 2004 | Issued |
Array
(
[id] => 7548615
[patent_doc_number] => RE042963
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2011-11-22
[patent_title] => 'Turbo interleaving apparatus and method'
[patent_app_type] => reissue
[patent_app_number] => 10/973100
[patent_app_country] => US
[patent_app_date] => 2004-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 12018
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/042/RE042963.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973100
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973100 | Turbo interleaving apparatus and method | Oct 24, 2004 | Issued |
Array
(
[id] => 816594
[patent_doc_number] => 07415644
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Self-repairing of microprocessor array structures'
[patent_app_type] => utility
[patent_app_number] => 10/971347
[patent_app_country] => US
[patent_app_date] => 2004-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4937
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/415/07415644.pdf
[firstpage_image] =>[orig_patent_app_number] => 10971347
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/971347 | Self-repairing of microprocessor array structures | Oct 21, 2004 | Issued |
Array
(
[id] => 5792367
[patent_doc_number] => 20060013048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Memory systems including defective block management and related methods'
[patent_app_type] => utility
[patent_app_number] => 10/969481
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5984
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20060013048.pdf
[firstpage_image] =>[orig_patent_app_number] => 10969481
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/969481 | Memory systems including defective block management and related methods | Oct 19, 2004 | Issued |
Array
(
[id] => 347068
[patent_doc_number] => 07500165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Systems and methods for controlling clock signals during scan testing integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/958555
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5463
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/500/07500165.pdf
[firstpage_image] =>[orig_patent_app_number] => 10958555
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/958555 | Systems and methods for controlling clock signals during scan testing integrated circuits | Oct 5, 2004 | Issued |
Array
(
[id] => 7215262
[patent_doc_number] => 20050044458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 10/949192
[patent_app_country] => US
[patent_app_date] => 2004-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9017
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20050044458.pdf
[firstpage_image] =>[orig_patent_app_number] => 10949192
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/949192 | Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory | Sep 26, 2004 | Issued |
Array
(
[id] => 5108810
[patent_doc_number] => 20070067688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Method and system for selectively masking test responses'
[patent_app_type] => utility
[patent_app_number] => 10/573083
[patent_app_country] => US
[patent_app_date] => 2004-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5437
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20070067688.pdf
[firstpage_image] =>[orig_patent_app_number] => 10573083
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/573083 | Method and system for selectively masking test responses | Sep 19, 2004 | Issued |
Array
(
[id] => 560498
[patent_doc_number] => 07178077
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Integrated circuit test apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/917403
[patent_app_country] => US
[patent_app_date] => 2004-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 23
[patent_no_of_words] => 16649
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/178/07178077.pdf
[firstpage_image] =>[orig_patent_app_number] => 10917403
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/917403 | Integrated circuit test apparatus | Aug 12, 2004 | Issued |
Array
(
[id] => 7123877
[patent_doc_number] => 20050015706
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Codeword for use in digital optical media and a method of generating therefor'
[patent_app_type] => utility
[patent_app_number] => 10/918559
[patent_app_country] => US
[patent_app_date] => 2004-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5948
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20050015706.pdf
[firstpage_image] =>[orig_patent_app_number] => 10918559
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/918559 | Codeword for use in digital optical media and a method of generating therefor | Aug 12, 2004 | Issued |
Array
(
[id] => 659543
[patent_doc_number] => 07111218
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Apparatus with self-test circuit'
[patent_app_type] => utility
[patent_app_number] => 10/915196
[patent_app_country] => US
[patent_app_date] => 2004-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2960
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/111/07111218.pdf
[firstpage_image] =>[orig_patent_app_number] => 10915196
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/915196 | Apparatus with self-test circuit | Aug 8, 2004 | Issued |
Array
(
[id] => 641283
[patent_doc_number] => 07127651
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-24
[patent_title] => 'Sampling rate converter for both oversampling and undersampling operation'
[patent_app_type] => utility
[patent_app_number] => 10/914306
[patent_app_country] => US
[patent_app_date] => 2004-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5987
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/127/07127651.pdf
[firstpage_image] =>[orig_patent_app_number] => 10914306
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/914306 | Sampling rate converter for both oversampling and undersampling operation | Aug 8, 2004 | Issued |
Array
(
[id] => 894817
[patent_doc_number] => 07350123
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-25
[patent_title] => 'Test apparatus, correction value managing method, and computer program'
[patent_app_type] => utility
[patent_app_number] => 10/913763
[patent_app_country] => US
[patent_app_date] => 2004-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7468
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/350/07350123.pdf
[firstpage_image] =>[orig_patent_app_number] => 10913763
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/913763 | Test apparatus, correction value managing method, and computer program | Aug 5, 2004 | Issued |
Array
(
[id] => 7036419
[patent_doc_number] => 20050034028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Device for testing smart card and method of testing the smart card'
[patent_app_type] => utility
[patent_app_number] => 10/912006
[patent_app_country] => US
[patent_app_date] => 2004-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3765
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20050034028.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912006
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912006 | Device for testing smart card and method of testing the smart card | Aug 4, 2004 | Issued |
Array
(
[id] => 5882638
[patent_doc_number] => 20060031721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-09
[patent_title] => 'Method and apparatus for system monitoring with reduced function cores'
[patent_app_type] => utility
[patent_app_number] => 10/912506
[patent_app_country] => US
[patent_app_date] => 2004-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3712
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20060031721.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912506
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912506 | Method and apparatus for system monitoring with reduced function cores | Aug 4, 2004 | Issued |
Array
(
[id] => 7123859
[patent_doc_number] => 20050015688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Phase shifter with reduced linear dependency'
[patent_app_type] => utility
[patent_app_number] => 10/911033
[patent_app_country] => US
[patent_app_date] => 2004-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9784
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20050015688.pdf
[firstpage_image] =>[orig_patent_app_number] => 10911033
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/911033 | Phase shifter with reduced linear dependency | Aug 2, 2004 | Issued |
Array
(
[id] => 5882650
[patent_doc_number] => 20060031733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-09
[patent_title] => 'Power-saving retention mode'
[patent_app_type] => utility
[patent_app_number] => 10/910440
[patent_app_country] => US
[patent_app_date] => 2004-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1733
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20060031733.pdf
[firstpage_image] =>[orig_patent_app_number] => 10910440
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/910440 | Power-saving retention mode | Aug 2, 2004 | Abandoned |
Array
(
[id] => 5592370
[patent_doc_number] => 20060041823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-23
[patent_title] => 'Method and apparatus for storing and retrieving multiple point-in-time consistent data sets'
[patent_app_type] => utility
[patent_app_number] => 10/910714
[patent_app_country] => US
[patent_app_date] => 2004-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4777
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20060041823.pdf
[firstpage_image] =>[orig_patent_app_number] => 10910714
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/910714 | Method and apparatus for storing and retrieving multiple point-in-time consistent data sets | Aug 2, 2004 | Issued |
Array
(
[id] => 641297
[patent_doc_number] => 07127659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-24
[patent_title] => 'Memory efficient LDPC decoding methods and apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/909753
[patent_app_country] => US
[patent_app_date] => 2004-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11812
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/127/07127659.pdf
[firstpage_image] =>[orig_patent_app_number] => 10909753
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/909753 | Memory efficient LDPC decoding methods and apparatus | Aug 1, 2004 | Issued |
Array
(
[id] => 609631
[patent_doc_number] => 07155653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-26
[patent_title] => 'System and method for testing electronic device performance'
[patent_app_type] => utility
[patent_app_number] => 10/909879
[patent_app_country] => US
[patent_app_date] => 2004-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3510
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/155/07155653.pdf
[firstpage_image] =>[orig_patent_app_number] => 10909879
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/909879 | System and method for testing electronic device performance | Aug 1, 2004 | Issued |