Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7013720 [patent_doc_number] => 20050066246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Lab-on-chip system and method and apparatus for manufacturing and operating same' [patent_app_type] => utility [patent_app_number] => 10/909920 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7456 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066246.pdf [firstpage_image] =>[orig_patent_app_number] => 10909920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909920
Lab-on-chip system and method and apparatus for manufacturing and operating same Aug 1, 2004 Issued
Array ( [id] => 7077321 [patent_doc_number] => 20050149787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Apparatus and method for testing MEGACO protocol' [patent_app_type] => utility [patent_app_number] => 10/910759 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5244 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149787.pdf [firstpage_image] =>[orig_patent_app_number] => 10910759 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910759
Apparatus and method for testing MEGACO protocol Aug 1, 2004 Issued
Array ( [id] => 7129379 [patent_doc_number] => 20050060627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Integrated test-on-chip system and method and apparatus for manufacturing and operating same' [patent_app_type] => utility [patent_app_number] => 10/909919 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8008 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20050060627.pdf [firstpage_image] =>[orig_patent_app_number] => 10909919 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909919
Integrated test-on-chip system and method and apparatus for manufacturing and operating same Aug 1, 2004 Issued
Array ( [id] => 302171 [patent_doc_number] => 07539910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Memory module test system for memory module including hub' [patent_app_type] => utility [patent_app_number] => 10/900140 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4135 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539910.pdf [firstpage_image] =>[orig_patent_app_number] => 10900140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/900140
Memory module test system for memory module including hub Jul 27, 2004 Issued
Array ( [id] => 836439 [patent_doc_number] => 07398456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Information encoding by shortened Reed-Solomon codes' [patent_app_type] => utility [patent_app_number] => 10/565280 [patent_app_country] => US [patent_app_date] => 2004-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7089 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/398/07398456.pdf [firstpage_image] =>[orig_patent_app_number] => 10565280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/565280
Information encoding by shortened Reed-Solomon codes Jul 20, 2004 Issued
Array ( [id] => 7262576 [patent_doc_number] => 20040261002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Iterative decoder employing multiple external code error checks to lower the error floor' [patent_app_type] => new [patent_app_number] => 10/892738 [patent_app_country] => US [patent_app_date] => 2004-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12367 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20040261002.pdf [firstpage_image] =>[orig_patent_app_number] => 10892738 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/892738
Iterative decoder employing multiple external code error checks to lower the error floor Jul 15, 2004 Issued
Array ( [id] => 816599 [patent_doc_number] => 07415648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method and system for testing a network interface' [patent_app_type] => utility [patent_app_number] => 10/888239 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415648.pdf [firstpage_image] =>[orig_patent_app_number] => 10888239 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/888239
Method and system for testing a network interface Jul 8, 2004 Issued
Array ( [id] => 6979700 [patent_doc_number] => 20050289418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Methods and apparatus for monitoring internal signals in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/880630 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4862 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289418.pdf [firstpage_image] =>[orig_patent_app_number] => 10880630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880630
Methods and apparatus for monitoring internal signals in an integrated circuit Jun 28, 2004 Issued
Array ( [id] => 7047118 [patent_doc_number] => 20050251713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Multi-port memory device having serial I/O interface' [patent_app_type] => utility [patent_app_number] => 10/877318 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6682 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20050251713.pdf [firstpage_image] =>[orig_patent_app_number] => 10877318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877318
Multi-port memory device having serial I/O interface Jun 24, 2004 Issued
Array ( [id] => 462561 [patent_doc_number] => 07246288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Integrated device with an improved BIST circuit for executing a structured test' [patent_app_type] => utility [patent_app_number] => 10/876372 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4257 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/246/07246288.pdf [firstpage_image] =>[orig_patent_app_number] => 10876372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876372
Integrated device with an improved BIST circuit for executing a structured test Jun 23, 2004 Issued
Array ( [id] => 898305 [patent_doc_number] => 07346823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-18 [patent_title] => 'Automatic built-in self-test of logic with seeding from on-chip memory' [patent_app_type] => utility [patent_app_number] => 10/876864 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5127 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346823.pdf [firstpage_image] =>[orig_patent_app_number] => 10876864 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876864
Automatic built-in self-test of logic with seeding from on-chip memory Jun 23, 2004 Issued
Array ( [id] => 7277570 [patent_doc_number] => 20040237021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture' [patent_app_type] => new [patent_app_number] => 10/877897 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6390 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20040237021.pdf [firstpage_image] =>[orig_patent_app_number] => 10877897 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877897
Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture Jun 23, 2004 Issued
Array ( [id] => 519106 [patent_doc_number] => 07203879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Built-in-test diagnostic and maintenance support system and process' [patent_app_type] => utility [patent_app_number] => 10/874620 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6405 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203879.pdf [firstpage_image] =>[orig_patent_app_number] => 10874620 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874620
Built-in-test diagnostic and maintenance support system and process Jun 21, 2004 Issued
Array ( [id] => 777996 [patent_doc_number] => 07003705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'Ethernet automatic protection switching' [patent_app_type] => utility [patent_app_number] => 10/871297 [patent_app_country] => US [patent_app_date] => 2004-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4436 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003705.pdf [firstpage_image] =>[orig_patent_app_number] => 10871297 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/871297
Ethernet automatic protection switching Jun 16, 2004 Issued
Array ( [id] => 384877 [patent_doc_number] => 07308625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-11 [patent_title] => 'Delay-fault testing method, related system and circuit' [patent_app_type] => utility [patent_app_number] => 10/559170 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/308/07308625.pdf [firstpage_image] =>[orig_patent_app_number] => 10559170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/559170
Delay-fault testing method, related system and circuit May 27, 2004 Issued
Array ( [id] => 615900 [patent_doc_number] => 07149944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Semiconductor integrated circuit device equipped with read sequencer and write sequencer' [patent_app_type] => utility [patent_app_number] => 10/852486 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 6986 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149944.pdf [firstpage_image] =>[orig_patent_app_number] => 10852486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/852486
Semiconductor integrated circuit device equipped with read sequencer and write sequencer May 24, 2004 Issued
Array ( [id] => 564526 [patent_doc_number] => 07168018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Apparatus and method for reducing test resources in testing DRAMs' [patent_app_type] => utility [patent_app_number] => 10/853573 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4650 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/168/07168018.pdf [firstpage_image] =>[orig_patent_app_number] => 10853573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853573
Apparatus and method for reducing test resources in testing DRAMs May 24, 2004 Issued
Array ( [id] => 645698 [patent_doc_number] => 07124342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/850460 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 69 [patent_no_of_words] => 14702 [patent_no_of_claims] => 102 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124342.pdf [firstpage_image] =>[orig_patent_app_number] => 10850460 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/850460
Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits May 20, 2004 Issued
Array ( [id] => 929659 [patent_doc_number] => 07315972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-01 [patent_title] => 'Method and apparatus for automated generation of expected value data for circuit designs' [patent_app_type] => utility [patent_app_number] => 10/850184 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4506 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315972.pdf [firstpage_image] =>[orig_patent_app_number] => 10850184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/850184
Method and apparatus for automated generation of expected value data for circuit designs May 19, 2004 Issued
Array ( [id] => 5108828 [patent_doc_number] => 20070067706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Testing ram address decoder for resistive open defects' [patent_app_type] => utility [patent_app_number] => 10/557375 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3617 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20070067706.pdf [firstpage_image] =>[orig_patent_app_number] => 10557375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/557375
Testing ram address decoder for resistive open defects May 13, 2004 Issued
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