Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9814596 [patent_doc_number] => 20150026541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'Iterative Decoding for Cascaded LDPC and TCM Coding' [patent_app_type] => utility [patent_app_number] => 14/336074 [patent_app_country] => US [patent_app_date] => 2014-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2417 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14336074 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/336074
Iterative decoding for cascaded LDPC and TCM coding Jul 20, 2014 Issued
Array ( [id] => 11228075 [patent_doc_number] => 09455803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Relay device and relay method' [patent_app_type] => utility [patent_app_number] => 14/330088 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7315 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330088 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330088
Relay device and relay method Jul 13, 2014 Issued
Array ( [id] => 11206236 [patent_doc_number] => 09435862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Integrated circuit device and method therefor' [patent_app_type] => utility [patent_app_number] => 14/330544 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5183 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330544 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330544
Integrated circuit device and method therefor Jul 13, 2014 Issued
Array ( [id] => 10667670 [patent_doc_number] => 20160013815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'Data Deduplication With Adaptive Erasure Code Redundancy' [patent_app_type] => utility [patent_app_number] => 14/326774 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7707 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326774
Data deduplication with adaptive erasure code redundancy Jul 8, 2014 Issued
Array ( [id] => 11201828 [patent_doc_number] => 09432053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-30 [patent_title] => 'High speed LDPC decoder' [patent_app_type] => utility [patent_app_number] => 14/325172 [patent_app_country] => US [patent_app_date] => 2014-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9606 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325172 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325172
High speed LDPC decoder Jul 6, 2014 Issued
Array ( [id] => 10492945 [patent_doc_number] => 20150377967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'DUTY CYCLE BASED TIMING MARGINING FOR I/O AC TIMING' [patent_app_type] => utility [patent_app_number] => 14/319528 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319528 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319528
Duty cycle based timing margining for I/O AC timing Jun 29, 2014 Issued
Array ( [id] => 9807980 [patent_doc_number] => 20150019925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/317108 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2298 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317108 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317108
Data storage device and flash memory control method Jun 26, 2014 Issued
Array ( [id] => 10496182 [patent_doc_number] => 20150381204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'ENCODER WITH TRANSFORM ARCHITECTURE FOR LDPC CODES OVER SUBFIELDS USING MESSAGE MAPPING' [patent_app_type] => utility [patent_app_number] => 14/316117 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10450 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316117
Encoder with transform architecture for LDPC codes over subfields using message mapping Jun 25, 2014 Issued
Array ( [id] => 9834543 [patent_doc_number] => 08943376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Position independent testing of circuits' [patent_app_type] => utility [patent_app_number] => 14/314430 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 54 [patent_no_of_words] => 27281 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314430 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314430
Position independent testing of circuits Jun 24, 2014 Issued
Array ( [id] => 10486700 [patent_doc_number] => 20150371720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SYSTEM AND METHOD FOR TESTING ADDRESS-SWAP FAULTS IN MULTIPORT MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/313192 [patent_app_country] => US [patent_app_date] => 2014-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14313192 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/313192
System and method for testing address-swap faults in multiport memories Jun 23, 2014 Issued
Array ( [id] => 11252043 [patent_doc_number] => 09477546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Methods and apparatus for optimizing lifespan of a storage device' [patent_app_type] => utility [patent_app_number] => 14/305383 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5912 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305383 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/305383
Methods and apparatus for optimizing lifespan of a storage device Jun 15, 2014 Issued
Array ( [id] => 10464790 [patent_doc_number] => 20150349806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'TECHNIQUE FOR ADAPTIVELY STRENGTHING ECC FOR FLASH CACHE' [patent_app_type] => utility [patent_app_number] => 14/289823 [patent_app_country] => US [patent_app_date] => 2014-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14289823 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/289823
Adaptively strengthening ECC for solid state cache May 28, 2014 Issued
Array ( [id] => 9879034 [patent_doc_number] => 08966330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-24 [patent_title] => 'Bad block reconfiguration in nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 14/290070 [patent_app_country] => US [patent_app_date] => 2014-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 9753 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14290070 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/290070
Bad block reconfiguration in nonvolatile memory May 28, 2014 Issued
Array ( [id] => 10454173 [patent_doc_number] => 20150339187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'SYSTEM AND METHOD OF STORING REDUNDANCY DATA' [patent_app_type] => utility [patent_app_number] => 14/284133 [patent_app_country] => US [patent_app_date] => 2014-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 16278 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14284133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/284133
System and method of storing redundancy data May 20, 2014 Issued
Array ( [id] => 9859951 [patent_doc_number] => 20150039968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'ERROR CODE MANAGEMENT IN SYSTEMS PERMITTING PARTIAL WRITES' [patent_app_type] => utility [patent_app_number] => 14/283517 [patent_app_country] => US [patent_app_date] => 2014-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4773 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14283517 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/283517
Error code management in systems permitting partial writes May 20, 2014 Issued
Array ( [id] => 9723106 [patent_doc_number] => 20140258807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'Decoding and Optimized Implementation of SECDED Codes over GF(q)' [patent_app_type] => utility [patent_app_number] => 14/281567 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5259 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281567 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281567
Decoding and optimized implementation of SECDED codes over GF(q) May 18, 2014 Issued
Array ( [id] => 9723098 [patent_doc_number] => 20140258799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION' [patent_app_type] => utility [patent_app_number] => 14/281189 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3687 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281189 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281189
IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION May 18, 2014 Abandoned
Array ( [id] => 11765634 [patent_doc_number] => 09374107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-21 [patent_title] => 'Time shared protograph LDPC decoder' [patent_app_type] => utility [patent_app_number] => 14/278749 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14278749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/278749
Time shared protograph LDPC decoder May 14, 2014 Issued
Array ( [id] => 10508265 [patent_doc_number] => 09236142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'System method and apparatus for screening a memory system' [patent_app_type] => utility [patent_app_number] => 14/275075 [patent_app_country] => US [patent_app_date] => 2014-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14275075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/275075
System method and apparatus for screening a memory system May 11, 2014 Issued
Array ( [id] => 10438583 [patent_doc_number] => 20150323595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'SYSTEM FOR REDUCING TEST TIME USING EMBEDDED TEST COMPRESSION CYCLE BALANCING' [patent_app_type] => utility [patent_app_number] => 14/272606 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272606
SYSTEM FOR REDUCING TEST TIME USING EMBEDDED TEST COMPRESSION CYCLE BALANCING May 7, 2014 Abandoned
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