David Ton

Array ( [id] => 671665 [patent_doc_number] => 07096396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Test system for circuits' [patent_app_type] => utility [patent_app_number] => 10/367771 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6143 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096396.pdf [firstpage_image] =>[orig_patent_app_number] => 10367771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1167045 [patent_doc_number] => 06772387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture' [patent_app_type] => B1 [patent_app_number] => 10/351099 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6373 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772387.pdf [firstpage_image] =>[orig_patent_app_number] => 10351099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6700449 [patent_doc_number] => 20030223329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'METHOD FOR MANAGING DEFECTS ON AN OPTICAL DISK' [patent_app_type] => new [patent_app_number] => 10/248110 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5324 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20030223329.pdf [firstpage_image] =>[orig_patent_app_number] => 10248110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7625682 [patent_doc_number] => 06769085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method for modifying a bit sequence in an ARQ restransmission, receiver and transmitter therefor' [patent_app_type] => B2 [patent_app_number] => 10/295899 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3700 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/769/06769085.pdf [firstpage_image] =>[orig_patent_app_number] => 10295899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6703190 [patent_doc_number] => 20030226070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Clock extraction circuit' [patent_app_type] => new [patent_app_number] => 10/294682 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3449 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20030226070.pdf [firstpage_image] =>[orig_patent_app_number] => 10294682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1001805 [patent_doc_number] => 06912677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Circuit for inspecting a data error' [patent_app_type] => utility [patent_app_number] => 10/294202 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5179 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912677.pdf [firstpage_image] =>[orig_patent_app_number] => 10294202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 999193 [patent_doc_number] => 06915469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'High speed vector access method from pattern memory for test systems' [patent_app_type] => utility [patent_app_number] => 10/294601 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4746 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915469.pdf [firstpage_image] =>[orig_patent_app_number] => 10294601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6631251 [patent_doc_number] => 20030102879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Device picker in handler' [patent_app_type] => new [patent_app_number] => 10/292584 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2904 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20030102879.pdf [firstpage_image] =>[orig_patent_app_number] => 10292584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 691061 [patent_doc_number] => 07080303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Method and system for computer based testing using plugins to expand functionality of a test driver' [patent_app_type] => utility [patent_app_number] => 10/292913 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 23703 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080303.pdf [firstpage_image] =>[orig_patent_app_number] => 10292913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 749647 [patent_doc_number] => 07032151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Systems and methods for testing integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/292976 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6345 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032151.pdf [firstpage_image] =>[orig_patent_app_number] => 10292976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6802460 [patent_doc_number] => 20030097625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Receiving circuit for receiving messages signals' [patent_app_type] => new [patent_app_number] => 10/294403 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2626 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20030097625.pdf [firstpage_image] =>[orig_patent_app_number] => 10294403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 777995 [patent_doc_number] => 07003704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Two-dimensional redundancy calculation' [patent_app_type] => utility [patent_app_number] => 10/292359 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3509 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003704.pdf [firstpage_image] =>[orig_patent_app_number] => 10292359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 950196 [patent_doc_number] => 06964002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Scan chain design using skewed clocks' [patent_app_type] => utility [patent_app_number] => 10/284008 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3485 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964002.pdf [firstpage_image] =>[orig_patent_app_number] => 10284008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 396854 [patent_doc_number] => 07299391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Circuit for control and observation of a scan chain' [patent_app_type] => utility [patent_app_number] => 10/281973 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2710 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299391.pdf [firstpage_image] =>[orig_patent_app_number] => 10281973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 950199 [patent_doc_number] => 06964004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Method and apparatus for testing a system-on-a-chip' [patent_app_type] => utility [patent_app_number] => 10/280543 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2675 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964004.pdf [firstpage_image] =>[orig_patent_app_number] => 10280543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7391602 [patent_doc_number] => 20040083330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Testing a multibank memory module' [patent_app_type] => new [patent_app_number] => 10/278685 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5481 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083330.pdf [firstpage_image] =>[orig_patent_app_number] => 10278685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 933535 [patent_doc_number] => 06981205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Data storage apparatus, read data processor, and read data processing method' [patent_app_type] => utility [patent_app_number] => 10/279305 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7109 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981205.pdf [firstpage_image] =>[orig_patent_app_number] => 10279305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7601880 [patent_doc_number] => 07237166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'System and method for evaluating a multiprocessor system using a random bus traffic generation technique' [patent_app_type] => utility [patent_app_number] => 10/278578 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2871 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237166.pdf [firstpage_image] =>[orig_patent_app_number] => 10278578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 771563 [patent_doc_number] => 07010734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method for microprocessor test insertion reduction' [patent_app_type] => utility [patent_app_number] => 10/277555 [patent_app_country] => US [patent_app_date] => 2002-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5291 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010734.pdf [firstpage_image] =>[orig_patent_app_number] => 10277555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6784545 [patent_doc_number] => 20030065993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Method of manufacturing Q-value and device therefor' [patent_app_type] => new [patent_app_number] => 10/274137 [patent_app_country] => US [patent_app_date] => 2002-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4897 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065993.pdf [firstpage_image] =>[orig_patent_app_number] => 10274137 [rel_patent_id] =>[rel_patent_doc_number] =>)