Search

David Ton

Examiner (ID: 3564, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2784, 2782, 2138, 2317, 2133
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5830550 [patent_doc_number] => 20020069382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Semiconductor integrated circuit device and method of testing it' [patent_app_type] => new [patent_app_number] => 09/996722 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9604 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069382.pdf [firstpage_image] =>[orig_patent_app_number] => 09996722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996722
Semiconductor integrated circuit device and method of testing it Nov 29, 2001 Issued
Array ( [id] => 1186015 [patent_doc_number] => 06745358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Enhanced fault coverage' [patent_app_type] => B1 [patent_app_number] => 09/997757 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3629 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745358.pdf [firstpage_image] =>[orig_patent_app_number] => 09997757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997757
Enhanced fault coverage Nov 29, 2001 Issued
Array ( [id] => 978880 [patent_doc_number] => 06934898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-23 [patent_title] => 'Test circuit topology reconfiguration and utilization techniques' [patent_app_type] => utility [patent_app_number] => 09/997784 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5133 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934898.pdf [firstpage_image] =>[orig_patent_app_number] => 09997784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997784
Test circuit topology reconfiguration and utilization techniques Nov 29, 2001 Issued
Array ( [id] => 1170614 [patent_doc_number] => 06766488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Compressing information using CAM for narrow bit pattern output' [patent_app_type] => B2 [patent_app_number] => 09/998769 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1236 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766488.pdf [firstpage_image] =>[orig_patent_app_number] => 09998769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998769
Compressing information using CAM for narrow bit pattern output Nov 28, 2001 Issued
Array ( [id] => 6766994 [patent_doc_number] => 20030101394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Method and apparatus for testing electronic components' [patent_app_type] => new [patent_app_number] => 09/998390 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2190 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101394.pdf [firstpage_image] =>[orig_patent_app_number] => 09998390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998390
Method and apparatus for testing electronic components Nov 28, 2001 Issued
Array ( [id] => 1183861 [patent_doc_number] => 06751768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits' [patent_app_type] => B2 [patent_app_number] => 09/997658 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1679 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751768.pdf [firstpage_image] =>[orig_patent_app_number] => 09997658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997658
Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits Nov 28, 2001 Issued
Array ( [id] => 6766988 [patent_doc_number] => 20030101388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'System and method for avoiding waiting repair analysis for semiconductor testing equipment' [patent_app_type] => new [patent_app_number] => 09/994707 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2307 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101388.pdf [firstpage_image] =>[orig_patent_app_number] => 09994707 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994707
System and method for avoiding waiting repair analysis for semiconductor testing equipment Nov 27, 2001 Abandoned
Array ( [id] => 6766993 [patent_doc_number] => 20030101393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Fast sampling test bench' [patent_app_type] => new [patent_app_number] => 09/996042 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3891 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101393.pdf [firstpage_image] =>[orig_patent_app_number] => 09996042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996042
Fast sampling test bench Nov 27, 2001 Issued
Array ( [id] => 6632924 [patent_doc_number] => 20020066056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory' [patent_app_type] => new [patent_app_number] => 09/994638 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9044 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066056.pdf [firstpage_image] =>[orig_patent_app_number] => 09994638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994638
Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory Nov 27, 2001 Issued
Array ( [id] => 6766991 [patent_doc_number] => 20030101391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'System for testing multiple devices on a single system and method thereof' [patent_app_type] => new [patent_app_number] => 09/995312 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7349 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101391.pdf [firstpage_image] =>[orig_patent_app_number] => 09995312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/995312
System for testing multiple devices on a single system and method thereof Nov 26, 2001 Issued
Array ( [id] => 1106356 [patent_doc_number] => 06816991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Built-in self-testing for double data rate input/output' [patent_app_type] => B2 [patent_app_number] => 09/996866 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4133 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816991.pdf [firstpage_image] =>[orig_patent_app_number] => 09996866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996866
Built-in self-testing for double data rate input/output Nov 26, 2001 Issued
Array ( [id] => 953413 [patent_doc_number] => 06961885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'System and method for testing video devices using a test fixture' [patent_app_type] => utility [patent_app_number] => 09/994261 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4553 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961885.pdf [firstpage_image] =>[orig_patent_app_number] => 09994261 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994261
System and method for testing video devices using a test fixture Nov 25, 2001 Issued
Array ( [id] => 947776 [patent_doc_number] => 06966020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'Identifying faulty programmable interconnect resources of field programmable gate arrays' [patent_app_type] => utility [patent_app_number] => 09/994299 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/966/06966020.pdf [firstpage_image] =>[orig_patent_app_number] => 09994299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994299
Identifying faulty programmable interconnect resources of field programmable gate arrays Nov 25, 2001 Issued
Array ( [id] => 1432422 [patent_doc_number] => 06505314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method and apparatus for processing defect addresses' [patent_app_type] => B2 [patent_app_number] => 10/034920 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10574 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505314.pdf [firstpage_image] =>[orig_patent_app_number] => 10034920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034920
Method and apparatus for processing defect addresses Nov 20, 2001 Issued
Array ( [id] => 6802461 [patent_doc_number] => 20030097626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Method and system for performing memory repair analysis' [patent_app_type] => new [patent_app_number] => 09/988518 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2158 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20030097626.pdf [firstpage_image] =>[orig_patent_app_number] => 09988518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988518
Method and system for performing memory repair analysis Nov 19, 2001 Issued
Array ( [id] => 6802462 [patent_doc_number] => 20030097627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Field repairable embedded memory in system-on-a-chip' [patent_app_type] => new [patent_app_number] => 09/988631 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4245 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20030097627.pdf [firstpage_image] =>[orig_patent_app_number] => 09988631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988631
Field repairable embedded memory in system-on-a-chip Nov 19, 2001 Issued
Array ( [id] => 782384 [patent_doc_number] => 06996758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Apparatus for testing an interconnecting logic fabric' [patent_app_type] => utility [patent_app_number] => 09/991410 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 13148 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996758.pdf [firstpage_image] =>[orig_patent_app_number] => 09991410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991410
Apparatus for testing an interconnecting logic fabric Nov 15, 2001 Issued
Array ( [id] => 794389 [patent_doc_number] => 06983405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'Method and apparatus for testing circuitry embedded within a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 09/991412 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 13140 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983405.pdf [firstpage_image] =>[orig_patent_app_number] => 09991412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991412
Method and apparatus for testing circuitry embedded within a field programmable gate array Nov 15, 2001 Issued
Array ( [id] => 6301657 [patent_doc_number] => 20020093358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Parallel logic device/circuit tester for testing plural logic devices/circuits and parallel memory chip repairing apparatus' [patent_app_type] => new [patent_app_number] => 09/992549 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4509 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093358.pdf [firstpage_image] =>[orig_patent_app_number] => 09992549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992549
Parallel logic device/circuit tester for testing plural logic devices/circuits and parallel memory chip repairing apparatus Nov 15, 2001 Abandoned
Array ( [id] => 6862730 [patent_doc_number] => 20030093738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Method and apparatus for performing error checking' [patent_app_type] => new [patent_app_number] => 09/998398 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1766 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20030093738.pdf [firstpage_image] =>[orig_patent_app_number] => 09998398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998398
Method and apparatus for performing error checking Nov 14, 2001 Issued
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