
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6226878
[patent_doc_number] => 20020004922
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[patent_issue_date] => 2002-01-10
[patent_title] => 'Method and apparatus for generating expect data from a captured bit pattern, and memory device using same'
[patent_app_type] => new
[patent_app_number] => 09/924139
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[pdf_file] => publications/A1/0004/20020004922.pdf
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Array
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[patent_issue_date] => 2002-09-12
[patent_title] => 'Signalling method in an incremental redundancy communication system whereby data blocks can be combined'
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Array
(
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[patent_title] => 'Circuit and method for testing an integrated circuit'
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Array
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[patent_issue_date] => 2004-06-01
[patent_title] => 'Dynamic logic scan gate method and apparatus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/901411 | Dynamic logic scan gate method and apparatus | Jul 8, 2001 | Issued |
Array
(
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[patent_title] => 'Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system'
[patent_app_type] => reissue
[patent_app_number] => 09/871978
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/871978 | Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system | Jun 3, 2001 | Issued |
Array
(
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[patent_title] => 'Communication system, and method of transmitting data therein'
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Array
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[patent_title] => 'Method and system for high-spread high-distance interleaving for turbo-codes'
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[patent_app_number] => 09/864396
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Array
(
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[patent_title] => 'Method and apparatus to facilitate self-testing of a system on a chip'
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Array
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[patent_title] => 'High-performance error-correcting codes with skew mapping'
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Array
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[patent_title] => 'Iteractive decoder employing multiple external code error checks to lower the error floor'
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Array
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Array
(
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Array
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Array
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Array
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Array
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