Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6226878 [patent_doc_number] => 20020004922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Method and apparatus for generating expect data from a captured bit pattern, and memory device using same' [patent_app_type] => new [patent_app_number] => 09/924139 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15825 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004922.pdf [firstpage_image] =>[orig_patent_app_number] => 09924139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924139
Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Aug 6, 2001 Issued
Array ( [id] => 6452710 [patent_doc_number] => 20020129312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Signalling method in an incremental redundancy communication system whereby data blocks can be combined' [patent_app_type] => new [patent_app_number] => 09/912934 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5013 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129312.pdf [firstpage_image] =>[orig_patent_app_number] => 09912934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/912934
Signalling method in an incremental redundancy communication system whereby data blocks can be combined Jul 24, 2001 Issued
Array ( [id] => 1402134 [patent_doc_number] => 06564351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Circuit and method for testing an integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/911687 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2996 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564351.pdf [firstpage_image] =>[orig_patent_app_number] => 09911687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911687
Circuit and method for testing an integrated circuit Jul 23, 2001 Issued
Array ( [id] => 1186013 [patent_doc_number] => 06745357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Dynamic logic scan gate method and apparatus' [patent_app_type] => B2 [patent_app_number] => 09/901411 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11488 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745357.pdf [firstpage_image] =>[orig_patent_app_number] => 09901411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901411
Dynamic logic scan gate method and apparatus Jul 8, 2001 Issued
Array ( [id] => 493316 [patent_doc_number] => RE039579 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system' [patent_app_type] => reissue [patent_app_number] => 09/871978 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 7742 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/039/RE039579.pdf [firstpage_image] =>[orig_patent_app_number] => 09871978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871978
Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system Jun 3, 2001 Issued
Array ( [id] => 7628130 [patent_doc_number] => 06820231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Communication system, and method of transmitting data therein' [patent_app_type] => B2 [patent_app_number] => 09/866592 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4337 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820231.pdf [firstpage_image] =>[orig_patent_app_number] => 09866592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866592
Communication system, and method of transmitting data therein May 29, 2001 Issued
Array ( [id] => 1201154 [patent_doc_number] => 06728927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method and system for high-spread high-distance interleaving for turbo-codes' [patent_app_type] => B2 [patent_app_number] => 09/864396 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8561 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728927.pdf [firstpage_image] =>[orig_patent_app_number] => 09864396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864396
Method and system for high-spread high-distance interleaving for turbo-codes May 24, 2001 Issued
Array ( [id] => 1059054 [patent_doc_number] => 06857092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Method and apparatus to facilitate self-testing of a system on a chip' [patent_app_type] => utility [patent_app_number] => 09/866080 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6687 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857092.pdf [firstpage_image] =>[orig_patent_app_number] => 09866080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866080
Method and apparatus to facilitate self-testing of a system on a chip May 24, 2001 Issued
Array ( [id] => 1210555 [patent_doc_number] => 06718508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'High-performance error-correcting codes with skew mapping' [patent_app_type] => B2 [patent_app_number] => 09/864253 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8507 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718508.pdf [firstpage_image] =>[orig_patent_app_number] => 09864253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864253
High-performance error-correcting codes with skew mapping May 24, 2001 Issued
Array ( [id] => 1112231 [patent_doc_number] => 06810502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Iteractive decoder employing multiple external code error checks to lower the error floor' [patent_app_type] => B2 [patent_app_number] => 09/865958 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810502.pdf [firstpage_image] =>[orig_patent_app_number] => 09865958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865958
Iteractive decoder employing multiple external code error checks to lower the error floor May 24, 2001 Issued
Array ( [id] => 995999 [patent_doc_number] => 06918072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Circuit and method for time-efficient memory repair' [patent_app_type] => utility [patent_app_number] => 09/864682 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 9994 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/918/06918072.pdf [firstpage_image] =>[orig_patent_app_number] => 09864682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864682
Circuit and method for time-efficient memory repair May 23, 2001 Issued
Array ( [id] => 6294487 [patent_doc_number] => 20020056063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Power saving feature during memory self-test' [patent_app_type] => new [patent_app_number] => 09/864789 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10658 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056063.pdf [firstpage_image] =>[orig_patent_app_number] => 09864789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864789
Power saving feature during memory self-test May 23, 2001 Abandoned
Array ( [id] => 1207011 [patent_doc_number] => 06721912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'Data carrier module having indication means for indicating the result of a test operation' [patent_app_type] => B2 [patent_app_number] => 09/864143 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2930 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721912.pdf [firstpage_image] =>[orig_patent_app_number] => 09864143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864143
Data carrier module having indication means for indicating the result of a test operation May 23, 2001 Issued
Array ( [id] => 6226885 [patent_doc_number] => 20020004924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Data transmission apparatus and method for an HARQ data communication system' [patent_app_type] => new [patent_app_number] => 09/864988 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5391 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004924.pdf [firstpage_image] =>[orig_patent_app_number] => 09864988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864988
Data transmission apparatus and method for an HARQ data communication system May 23, 2001 Issued
Array ( [id] => 1201134 [patent_doc_number] => 06728916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Hierarchical built-in self-test for system-on-chip design' [patent_app_type] => B2 [patent_app_number] => 09/863952 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2740 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728916.pdf [firstpage_image] =>[orig_patent_app_number] => 09863952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863952
Hierarchical built-in self-test for system-on-chip design May 22, 2001 Issued
Array ( [id] => 1248960 [patent_doc_number] => 06678852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Semiconductor device testing apparatus' [patent_app_type] => B2 [patent_app_number] => 09/865811 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3933 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678852.pdf [firstpage_image] =>[orig_patent_app_number] => 09865811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865811
Semiconductor device testing apparatus May 22, 2001 Issued
Array ( [id] => 6593580 [patent_doc_number] => 20020015419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Data transmission apparatus and method for an HARQ data communication system' [patent_app_type] => new [patent_app_number] => 09/863110 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10619 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20020015419.pdf [firstpage_image] =>[orig_patent_app_number] => 09863110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863110
Data transmission apparatus and method for an HARQ data communication system May 21, 2001 Issued
Array ( [id] => 6461469 [patent_doc_number] => 20020178417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Communication channel optimization using forward error correction statistics' [patent_app_type] => new [patent_app_number] => 09/863043 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7133 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178417.pdf [firstpage_image] =>[orig_patent_app_number] => 09863043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863043
Communication channel optimization using forward error correction statistics May 21, 2001 Abandoned
Array ( [id] => 992816 [patent_doc_number] => 06920598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'System and method for error recovery using NAKs' [patent_app_type] => utility [patent_app_number] => 09/861740 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 3907 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920598.pdf [firstpage_image] =>[orig_patent_app_number] => 09861740 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861740
System and method for error recovery using NAKs May 20, 2001 Issued
Array ( [id] => 1186732 [patent_doc_number] => 06738939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method and apparatus for fault tolerant and flexible test signature generator' [patent_app_type] => B2 [patent_app_number] => 09/862407 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1817 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738939.pdf [firstpage_image] =>[orig_patent_app_number] => 09862407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862407
Method and apparatus for fault tolerant and flexible test signature generator May 20, 2001 Issued
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