Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1234625 [patent_doc_number] => 06697996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Multi-dimensional packet recovery system and method' [patent_app_type] => B2 [patent_app_number] => 09/860270 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3604 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697996.pdf [firstpage_image] =>[orig_patent_app_number] => 09860270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860270
Multi-dimensional packet recovery system and method May 17, 2001 Issued
Array ( [id] => 1210520 [patent_doc_number] => 06718493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method and apparatus for selection of ARQ parameters and estimation of improved communications' [patent_app_type] => B1 [patent_app_number] => 09/859867 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 10425 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718493.pdf [firstpage_image] =>[orig_patent_app_number] => 09859867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/859867
Method and apparatus for selection of ARQ parameters and estimation of improved communications May 16, 2001 Issued
Array ( [id] => 5816246 [patent_doc_number] => 20020040454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Self-test ram using external synchronous clock' [patent_app_type] => new [patent_app_number] => 09/837116 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4401 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20020040454.pdf [firstpage_image] =>[orig_patent_app_number] => 09837116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/837116
Self-test RAM using external synchronous clock Apr 16, 2001 Issued
Array ( [id] => 1066872 [patent_doc_number] => 06851086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Transmitter, receiver, and coding scheme to increase data rate and decrease bit error rate of an optical data link' [patent_app_type] => utility [patent_app_number] => 09/821758 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 53 [patent_no_of_words] => 23252 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851086.pdf [firstpage_image] =>[orig_patent_app_number] => 09821758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821758
Transmitter, receiver, and coding scheme to increase data rate and decrease bit error rate of an optical data link Mar 29, 2001 Issued
Array ( [id] => 778019 [patent_doc_number] => 07003715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'Galois field multiply accumulator' [patent_app_type] => utility [patent_app_number] => 09/822733 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 14645 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003715.pdf [firstpage_image] =>[orig_patent_app_number] => 09822733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/822733
Galois field multiply accumulator Mar 29, 2001 Issued
Array ( [id] => 794411 [patent_doc_number] => 06983414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'Error insertion circuit for SONET forward error correction' [patent_app_type] => utility [patent_app_number] => 09/821948 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 17838 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983414.pdf [firstpage_image] =>[orig_patent_app_number] => 09821948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821948
Error insertion circuit for SONET forward error correction Mar 29, 2001 Issued
Array ( [id] => 1011503 [patent_doc_number] => 06901548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Coding apparatus, coding method and recording medium having coded program recorded therein, and decoding apparatus, decoding method and recording medium having decoded program recorded therein' [patent_app_type] => utility [patent_app_number] => 09/821008 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 20208 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901548.pdf [firstpage_image] =>[orig_patent_app_number] => 09821008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821008
Coding apparatus, coding method and recording medium having coded program recorded therein, and decoding apparatus, decoding method and recording medium having decoded program recorded therein Mar 28, 2001 Issued
Array ( [id] => 5910676 [patent_doc_number] => 20020144211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Method and program product for detecting bus conflict and floating bus conditions in circuit designs' [patent_app_type] => new [patent_app_number] => 09/817299 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6392 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144211.pdf [firstpage_image] =>[orig_patent_app_number] => 09817299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817299
Method and program product for detecting bus conflict and floating bus conditions in circuit designs Mar 26, 2001 Issued
Array ( [id] => 1319384 [patent_doc_number] => 06618829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Communication system, a synchronization circuit, a method of communicating a data signal, and methods of synchronizing with a data signal' [patent_app_type] => B2 [patent_app_number] => 09/817819 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7184 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618829.pdf [firstpage_image] =>[orig_patent_app_number] => 09817819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817819
Communication system, a synchronization circuit, a method of communicating a data signal, and methods of synchronizing with a data signal Mar 25, 2001 Issued
Array ( [id] => 5803602 [patent_doc_number] => 20020010887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'IC with IP core and user-added scan register' [patent_app_type] => new [patent_app_number] => 09/812220 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3415 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010887.pdf [firstpage_image] =>[orig_patent_app_number] => 09812220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812220
IC with IP core and user-added scan register Mar 18, 2001 Issued
Array ( [id] => 6900408 [patent_doc_number] => 20010010084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Memory fault diagnosis and data restoration method, and memory apparatus using the same' [patent_app_type] => new [patent_app_number] => 09/803772 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9192 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010084.pdf [firstpage_image] =>[orig_patent_app_number] => 09803772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803772
Memory fault diagnosis and data restoration method, and memory apparatus using the same Mar 11, 2001 Abandoned
Array ( [id] => 1284936 [patent_doc_number] => 06651202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Built-in self repair circuitry utilizing permanent record of defects' [patent_app_type] => B1 [patent_app_number] => 09/802198 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5845 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651202.pdf [firstpage_image] =>[orig_patent_app_number] => 09802198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802198
Built-in self repair circuitry utilizing permanent record of defects Mar 7, 2001 Issued
Array ( [id] => 5856770 [patent_doc_number] => 20020121886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Methods to make DRAM fully compatible with SRAM' [patent_app_type] => new [patent_app_number] => 09/790356 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6585 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20020121886.pdf [firstpage_image] =>[orig_patent_app_number] => 09790356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790356
Methods to make DRAM fully compatible with SRAM Feb 19, 2001 Abandoned
Array ( [id] => 1075203 [patent_doc_number] => 06839871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Method for transparent multiplexing of SONET/ SDH streams' [patent_app_type] => utility [patent_app_number] => 09/779190 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6238 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839871.pdf [firstpage_image] =>[orig_patent_app_number] => 09779190 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779190
Method for transparent multiplexing of SONET/ SDH streams Feb 7, 2001 Issued
Array ( [id] => 7063493 [patent_doc_number] => 20050005208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Method and apparatus for checking the resistance of programmable elements' [patent_app_type] => utility [patent_app_number] => 09/777036 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4403 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20050005208.pdf [firstpage_image] =>[orig_patent_app_number] => 09777036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777036
Method and apparatus for checking the resistance of programmable elements Feb 4, 2001 Issued
Array ( [id] => 6962937 [patent_doc_number] => 20010013111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip' [patent_app_type] => new [patent_app_number] => 09/768637 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6216 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013111.pdf [firstpage_image] =>[orig_patent_app_number] => 09768637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768637
Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip Jan 23, 2001 Issued
Array ( [id] => 6902249 [patent_doc_number] => 20010001158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'Memory array organization' [patent_app_type] => new-utility [patent_app_number] => 09/752519 [patent_app_country] => US [patent_app_date] => 2001-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2592 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001158.pdf [firstpage_image] =>[orig_patent_app_number] => 09752519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752519
Memory array organization Jan 2, 2001 Issued
Array ( [id] => 1421809 [patent_doc_number] => 06543024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Write format for digital data storage' [patent_app_type] => B2 [patent_app_number] => 09/746876 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10050 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/543/06543024.pdf [firstpage_image] =>[orig_patent_app_number] => 09746876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746876
Write format for digital data storage Dec 21, 2000 Issued
Array ( [id] => 1407563 [patent_doc_number] => 06560728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Layout for semiconductor memory device having a plurality of rows and columns of circuit cells divided into first and second planes that are not simultaneously active' [patent_app_type] => B2 [patent_app_number] => 09/747352 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9333 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560728.pdf [firstpage_image] =>[orig_patent_app_number] => 09747352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747352
Layout for semiconductor memory device having a plurality of rows and columns of circuit cells divided into first and second planes that are not simultaneously active Dec 18, 2000 Issued
Array ( [id] => 6988820 [patent_doc_number] => 20010037482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture' [patent_app_type] => new [patent_app_number] => 09/734784 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6398 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037482.pdf [firstpage_image] =>[orig_patent_app_number] => 09734784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734784
Cyclic redundancy checking of a field programmable gate array having a SRAM memory architecture Dec 10, 2000 Issued
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