Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1431973 [patent_doc_number] => 06516432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'AC scan diagnostic method' [patent_app_type] => B1 [patent_app_number] => 09/469699 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4346 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516432.pdf [firstpage_image] =>[orig_patent_app_number] => 09469699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469699
AC scan diagnostic method Dec 21, 1999 Issued
Array ( [id] => 1297407 [patent_doc_number] => 06634006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Packet data communication device' [patent_app_type] => B1 [patent_app_number] => 09/469394 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3051 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/634/06634006.pdf [firstpage_image] =>[orig_patent_app_number] => 09469394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469394
Packet data communication device Dec 21, 1999 Issued
Array ( [id] => 1430632 [patent_doc_number] => 06526530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method and apparatus for encoding data incorporating check bits and maximum transition run constraint' [patent_app_type] => B1 [patent_app_number] => 09/470170 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3660 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 460 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526530.pdf [firstpage_image] =>[orig_patent_app_number] => 09470170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470170
Method and apparatus for encoding data incorporating check bits and maximum transition run constraint Dec 21, 1999 Issued
Array ( [id] => 1525017 [patent_doc_number] => 06415405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method and apparatus for scan of synchronized dynamic logic using embedded scan gates' [patent_app_type] => B1 [patent_app_number] => 09/468759 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415405.pdf [firstpage_image] =>[orig_patent_app_number] => 09468759 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468759
Method and apparatus for scan of synchronized dynamic logic using embedded scan gates Dec 20, 1999 Issued
Array ( [id] => 1260619 [patent_doc_number] => 06668343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Interleaving/deinterleaving device and method for communication system' [patent_app_type] => B1 [patent_app_number] => 09/468568 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6470 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668343.pdf [firstpage_image] =>[orig_patent_app_number] => 09468568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468568
Interleaving/deinterleaving device and method for communication system Dec 20, 1999 Issued
Array ( [id] => 1325782 [patent_doc_number] => 06615380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Dynamic scan chains and test pattern generation methodologies therefor' [patent_app_type] => B1 [patent_app_number] => 09/469729 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6387 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615380.pdf [firstpage_image] =>[orig_patent_app_number] => 09469729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469729
Dynamic scan chains and test pattern generation methodologies therefor Dec 20, 1999 Issued
Array ( [id] => 1539385 [patent_doc_number] => 06412085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state' [patent_app_type] => B1 [patent_app_number] => 09/468760 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412085.pdf [firstpage_image] =>[orig_patent_app_number] => 09468760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468760
Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state Dec 20, 1999 Issued
Array ( [id] => 1309257 [patent_doc_number] => 06629274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer' [patent_app_type] => B1 [patent_app_number] => 09/470091 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629274.pdf [firstpage_image] =>[orig_patent_app_number] => 09470091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470091
Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer Dec 20, 1999 Issued
Array ( [id] => 1431980 [patent_doc_number] => 06516434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Application-specific integrated circuit (ASIC) for use in communication facilities of a digital network' [patent_app_type] => B1 [patent_app_number] => 09/467241 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3603 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516434.pdf [firstpage_image] =>[orig_patent_app_number] => 09467241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/467241
Application-specific integrated circuit (ASIC) for use in communication facilities of a digital network Dec 19, 1999 Issued
Array ( [id] => 1432421 [patent_doc_number] => 06505313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Multi-condition BISR test mode for memories with redundancy' [patent_app_type] => B1 [patent_app_number] => 09/466389 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3789 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505313.pdf [firstpage_image] =>[orig_patent_app_number] => 09466389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466389
Multi-condition BISR test mode for memories with redundancy Dec 16, 1999 Issued
Array ( [id] => 1248962 [patent_doc_number] => 06678853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method and apparatus for generating random code' [patent_app_type] => B1 [patent_app_number] => 09/466503 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2971 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678853.pdf [firstpage_image] =>[orig_patent_app_number] => 09466503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466503
Method and apparatus for generating random code Dec 16, 1999 Issued
Array ( [id] => 1472130 [patent_doc_number] => 06460162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Product code iterative decoding' [patent_app_type] => B1 [patent_app_number] => 09/446152 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6797 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460162.pdf [firstpage_image] =>[orig_patent_app_number] => 09446152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/446152
Product code iterative decoding Dec 16, 1999 Issued
Array ( [id] => 1521872 [patent_doc_number] => 06502218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Deferred correction of a single bit storage error in a cache tag array' [patent_app_type] => B1 [patent_app_number] => 09/461243 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3324 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502218.pdf [firstpage_image] =>[orig_patent_app_number] => 09461243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461243
Deferred correction of a single bit storage error in a cache tag array Dec 15, 1999 Issued
Array ( [id] => 1431971 [patent_doc_number] => 06516430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Test circuit for semiconductor device with multiple memory circuits' [patent_app_type] => B1 [patent_app_number] => 09/461403 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 13995 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516430.pdf [firstpage_image] =>[orig_patent_app_number] => 09461403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461403
Test circuit for semiconductor device with multiple memory circuits Dec 14, 1999 Issued
Array ( [id] => 1431590 [patent_doc_number] => 06519726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Semiconductor device and testing method of the same' [patent_app_type] => B1 [patent_app_number] => 09/461200 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9538 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519726.pdf [firstpage_image] =>[orig_patent_app_number] => 09461200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461200
Semiconductor device and testing method of the same Dec 14, 1999 Issued
Array ( [id] => 1567716 [patent_doc_number] => 06438728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Error character generation' [patent_app_type] => B1 [patent_app_number] => 09/461395 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4391 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438728.pdf [firstpage_image] =>[orig_patent_app_number] => 09461395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461395
Error character generation Dec 14, 1999 Issued
Array ( [id] => 1509124 [patent_doc_number] => 06467056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Semiconductor integrated circuit and method of checking memory' [patent_app_type] => B1 [patent_app_number] => 09/461401 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12742 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467056.pdf [firstpage_image] =>[orig_patent_app_number] => 09461401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461401
Semiconductor integrated circuit and method of checking memory Dec 14, 1999 Issued
Array ( [id] => 1513428 [patent_doc_number] => 06442708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Fault localization and health indication for a controller area network' [patent_app_type] => B1 [patent_app_number] => 09/461662 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3239 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442708.pdf [firstpage_image] =>[orig_patent_app_number] => 09461662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461662
Fault localization and health indication for a controller area network Dec 13, 1999 Issued
Array ( [id] => 1419463 [patent_doc_number] => 06546514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Integrated circuit analysis and design involving defective circuit element replacement on a netlist' [patent_app_type] => B1 [patent_app_number] => 09/460254 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546514.pdf [firstpage_image] =>[orig_patent_app_number] => 09460254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460254
Integrated circuit analysis and design involving defective circuit element replacement on a netlist Dec 12, 1999 Issued
09/458839 TEST METHOD AND ARCHITECTURE FOR CIRCUITS HAVING INPUTS Dec 12, 1999 Abandoned
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