
David Ton
Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2782, 2117, 2784, 2317, 2133, 2138 |
| Total Applications | 1397 |
| Issued Applications | 1295 |
| Pending Applications | 31 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1431973
[patent_doc_number] => 06516432
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'AC scan diagnostic method'
[patent_app_type] => B1
[patent_app_number] => 09/469699
[patent_app_country] => US
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[pdf_file] => patents/06/516/06516432.pdf
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Array
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[patent_issue_date] => 2003-10-14
[patent_title] => 'Packet data communication device'
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Array
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[patent_title] => 'Method and apparatus for encoding data incorporating check bits and maximum transition run constraint'
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Array
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[patent_title] => 'Method and apparatus for scan of synchronized dynamic logic using embedded scan gates'
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Array
(
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[patent_title] => 'Interleaving/deinterleaving device and method for communication system'
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Array
(
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[patent_title] => 'Dynamic scan chains and test pattern generation methodologies therefor'
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Array
(
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[patent_title] => 'Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state'
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[patent_app_number] => 09/468760
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Array
(
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[patent_issue_date] => 2003-09-30
[patent_title] => 'Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer'
[patent_app_type] => B1
[patent_app_number] => 09/470091
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Array
(
[id] => 1431980
[patent_doc_number] => 06516434
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[patent_title] => 'Application-specific integrated circuit (ASIC) for use in communication facilities of a digital network'
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[patent_app_number] => 09/467241
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/467241 | Application-specific integrated circuit (ASIC) for use in communication facilities of a digital network | Dec 19, 1999 | Issued |
Array
(
[id] => 1432421
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[patent_issue_date] => 2003-01-07
[patent_title] => 'Multi-condition BISR test mode for memories with redundancy'
[patent_app_type] => B1
[patent_app_number] => 09/466389
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Array
(
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[patent_title] => 'Method and apparatus for generating random code'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
(
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[patent_title] => 'Integrated circuit analysis and design involving defective circuit element replacement on a netlist'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/460254 | Integrated circuit analysis and design involving defective circuit element replacement on a netlist | Dec 12, 1999 | Issued |
| 09/458839 | TEST METHOD AND ARCHITECTURE FOR CIRCUITS HAVING INPUTS | Dec 12, 1999 | Abandoned |