Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1250303 [patent_doc_number] => 06675327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Communications system including lower rate parallel electronics with skew compensation and associated methods' [patent_app_type] => B1 [patent_app_number] => 09/460165 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8701 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675327.pdf [firstpage_image] =>[orig_patent_app_number] => 09460165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460165
Communications system including lower rate parallel electronics with skew compensation and associated methods Dec 12, 1999 Issued
Array ( [id] => 1596078 [patent_doc_number] => 06484281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Software-based simulation system capable of simulating the combined functionality of a north bridge test module and a south bridge test module' [patent_app_type] => B1 [patent_app_number] => 09/459763 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4421 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484281.pdf [firstpage_image] =>[orig_patent_app_number] => 09459763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459763
Software-based simulation system capable of simulating the combined functionality of a north bridge test module and a south bridge test module Dec 12, 1999 Issued
Array ( [id] => 1248942 [patent_doc_number] => 06678842 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Communications system and associated deskewing methods' [patent_app_type] => B1 [patent_app_number] => 09/459848 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8574 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678842.pdf [firstpage_image] =>[orig_patent_app_number] => 09459848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459848
Communications system and associated deskewing methods Dec 12, 1999 Issued
Array ( [id] => 1526596 [patent_doc_number] => 06353913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-05 [patent_title] => 'Modulation detection method and apparatus' [patent_app_type] => B2 [patent_app_number] => 09/439805 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3566 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353913.pdf [firstpage_image] =>[orig_patent_app_number] => 09439805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439805
Modulation detection method and apparatus Nov 11, 1999 Issued
Array ( [id] => 4101502 [patent_doc_number] => 06163860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Layout for a semiconductor memory device having redundant elements' [patent_app_type] => 1 [patent_app_number] => 9/415472 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 7 [patent_no_of_words] => 9076 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163860.pdf [firstpage_image] =>[orig_patent_app_number] => 415472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415472
Layout for a semiconductor memory device having redundant elements Oct 7, 1999 Issued
Array ( [id] => 1240959 [patent_doc_number] => 06691261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'De-interleaver and method of de-interleaving' [patent_app_type] => B1 [patent_app_number] => 09/411156 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691261.pdf [firstpage_image] =>[orig_patent_app_number] => 09411156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411156
De-interleaver and method of de-interleaving Sep 30, 1999 Issued
09/406206 METHOD OF MANUFACTURING Q-VALUE AND DEVICE THEREFOR Sep 27, 1999 Abandoned
Array ( [id] => 1298338 [patent_doc_number] => 06631491 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Interleaving method, interleaving apparatus, and recording medium in which interleave pattern generating program is recorded' [patent_app_type] => B1 [patent_app_number] => 09/341113 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 53 [patent_no_of_words] => 16271 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631491.pdf [firstpage_image] =>[orig_patent_app_number] => 09341113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/341113
Interleaving method, interleaving apparatus, and recording medium in which interleave pattern generating program is recorded Aug 19, 1999 Issued
Array ( [id] => 1475165 [patent_doc_number] => 06408417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method and apparatus for correcting soft errors in digital data' [patent_app_type] => B1 [patent_app_number] => 09/376702 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2173 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408417.pdf [firstpage_image] =>[orig_patent_app_number] => 09376702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376702
Method and apparatus for correcting soft errors in digital data Aug 16, 1999 Issued
Array ( [id] => 1444192 [patent_doc_number] => 06496950 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Testing content addressable static memories' [patent_app_type] => B1 [patent_app_number] => 09/372275 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15144 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496950.pdf [firstpage_image] =>[orig_patent_app_number] => 09372275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372275
Testing content addressable static memories Aug 10, 1999 Issued
09/369859 MEMORY TEST SYSTEM WITH A MEANS FOR TEST SEQUENCE OPTIMISATION AND A METHOD OF ITS OPERATION Aug 8, 1999 Abandoned
Array ( [id] => 4415785 [patent_doc_number] => 06310564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method and apparatus for compressively coding/decoding digital data to reduce the use of band-width or storage space' [patent_app_type] => 1 [patent_app_number] => 9/369204 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 13104 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310564.pdf [firstpage_image] =>[orig_patent_app_number] => 369204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369204
Method and apparatus for compressively coding/decoding digital data to reduce the use of band-width or storage space Aug 5, 1999 Issued
Array ( [id] => 1424071 [patent_doc_number] => 06539512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Interleaving method and circuit for high density recording medium' [patent_app_type] => B1 [patent_app_number] => 09/366755 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6099 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539512.pdf [firstpage_image] =>[orig_patent_app_number] => 09366755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/366755
Interleaving method and circuit for high density recording medium Aug 3, 1999 Issued
Array ( [id] => 1407682 [patent_doc_number] => 06560735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Methods and apparatus for testing integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/366388 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3607 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560735.pdf [firstpage_image] =>[orig_patent_app_number] => 09366388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/366388
Methods and apparatus for testing integrated circuits Aug 2, 1999 Issued
Array ( [id] => 1402061 [patent_doc_number] => 06564347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method and apparatus for testing an integrated circuit using an on-chip logic analyzer unit' [patent_app_type] => B1 [patent_app_number] => 09/364326 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564347.pdf [firstpage_image] =>[orig_patent_app_number] => 09364326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364326
Method and apparatus for testing an integrated circuit using an on-chip logic analyzer unit Jul 28, 1999 Issued
Array ( [id] => 1539396 [patent_doc_number] => 06412087 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Pattern data transfer circuit' [patent_app_type] => B1 [patent_app_number] => 09/362975 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4340 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412087.pdf [firstpage_image] =>[orig_patent_app_number] => 09362975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362975
Pattern data transfer circuit Jul 27, 1999 Issued
Array ( [id] => 7638561 [patent_doc_number] => 06397360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method and apparatus for generating a fibre channel compliant frame' [patent_app_type] => B1 [patent_app_number] => 09/363130 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2442 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397360.pdf [firstpage_image] =>[orig_patent_app_number] => 09363130 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363130
Method and apparatus for generating a fibre channel compliant frame Jul 27, 1999 Issued
Array ( [id] => 4424791 [patent_doc_number] => 06266794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Circuit and method for testing an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/361848 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266794.pdf [firstpage_image] =>[orig_patent_app_number] => 361848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361848
Circuit and method for testing an integrated circuit Jul 26, 1999 Issued
Array ( [id] => 1521868 [patent_doc_number] => 06502217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and apparatus for randomizing sector addresses in a disk storage device' [patent_app_type] => B1 [patent_app_number] => 09/361628 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7384 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502217.pdf [firstpage_image] =>[orig_patent_app_number] => 09361628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361628
Method and apparatus for randomizing sector addresses in a disk storage device Jul 26, 1999 Issued
Array ( [id] => 4400983 [patent_doc_number] => 06304989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Built-in spare row and column replacement analysis system for embedded memories' [patent_app_type] => 1 [patent_app_number] => 9/358689 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 40 [patent_no_of_words] => 8273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304989.pdf [firstpage_image] =>[orig_patent_app_number] => 358689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358689
Built-in spare row and column replacement analysis system for embedded memories Jul 20, 1999 Issued
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