Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4335936 [patent_doc_number] => 06243840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Self-test ram using external synchronous clock' [patent_app_type] => 1 [patent_app_number] => 9/347933 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4321 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243840.pdf [firstpage_image] =>[orig_patent_app_number] => 347933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347933
Self-test ram using external synchronous clock Jul 5, 1999 Issued
Array ( [id] => 1460205 [patent_doc_number] => 06463559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Non-volatile fault indicator' [patent_app_type] => B1 [patent_app_number] => 09/343451 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2685 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463559.pdf [firstpage_image] =>[orig_patent_app_number] => 09343451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343451
Non-volatile fault indicator Jun 29, 1999 Issued
Array ( [id] => 1432423 [patent_doc_number] => 06505315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Semiconductor device testing apparatus and signal output apparatus for outputting a differential signal to a test semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/338606 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4259 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505315.pdf [firstpage_image] =>[orig_patent_app_number] => 09338606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338606
Semiconductor device testing apparatus and signal output apparatus for outputting a differential signal to a test semiconductor device Jun 22, 1999 Issued
Array ( [id] => 1525009 [patent_doc_number] => 06415403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Programmable built in self test for embedded DRAM' [patent_app_type] => B1 [patent_app_number] => 09/334569 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3536 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415403.pdf [firstpage_image] =>[orig_patent_app_number] => 09334569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334569
Programmable built in self test for embedded DRAM Jun 20, 1999 Issued
Array ( [id] => 1501739 [patent_doc_number] => 06405337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Systems, methods and computer program products for adjusting a timeout for message retransmission based on measured round-trip communications delays' [patent_app_type] => B1 [patent_app_number] => 09/337182 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3369 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405337.pdf [firstpage_image] =>[orig_patent_app_number] => 09337182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337182
Systems, methods and computer program products for adjusting a timeout for message retransmission based on measured round-trip communications delays Jun 20, 1999 Issued
Array ( [id] => 1472117 [patent_doc_number] => 06460158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Transmission system with adaptive channel encoder and decoder' [patent_app_type] => B1 [patent_app_number] => 09/316996 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4835 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460158.pdf [firstpage_image] =>[orig_patent_app_number] => 09316996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316996
Transmission system with adaptive channel encoder and decoder May 23, 1999 Issued
Array ( [id] => 1553208 [patent_doc_number] => 06446238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'System and method for updating microcode stored in a non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 09/316756 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3693 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446238.pdf [firstpage_image] =>[orig_patent_app_number] => 09316756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316756
System and method for updating microcode stored in a non-volatile memory May 20, 1999 Issued
Array ( [id] => 1417472 [patent_doc_number] => 06532562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Receiver-driven layered error correction multicast over heterogeneous packet networks' [patent_app_type] => B1 [patent_app_number] => 09/316869 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12038 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532562.pdf [firstpage_image] =>[orig_patent_app_number] => 09316869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316869
Receiver-driven layered error correction multicast over heterogeneous packet networks May 20, 1999 Issued
Array ( [id] => 1354076 [patent_doc_number] => 06594798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Receiver-driven layered error correction multicast over heterogeneous packet networks' [patent_app_type] => B1 [patent_app_number] => 09/316696 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13047 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594798.pdf [firstpage_image] =>[orig_patent_app_number] => 09316696 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316696
Receiver-driven layered error correction multicast over heterogeneous packet networks May 20, 1999 Issued
Array ( [id] => 1431994 [patent_doc_number] => 06516440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Printer and a control method for saving data from volatile to nonvolatile memory in the printer' [patent_app_type] => B1 [patent_app_number] => 09/312039 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6856 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516440.pdf [firstpage_image] =>[orig_patent_app_number] => 09312039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312039
Printer and a control method for saving data from volatile to nonvolatile memory in the printer May 13, 1999 Issued
Array ( [id] => 1604533 [patent_doc_number] => 06434719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Error correction using reliability values for data matrix' [patent_app_type] => B1 [patent_app_number] => 09/307282 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5900 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434719.pdf [firstpage_image] =>[orig_patent_app_number] => 09307282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307282
Error correction using reliability values for data matrix May 6, 1999 Issued
Array ( [id] => 1429407 [patent_doc_number] => 06513141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Sampled amplitude read channel employing a trellis sequence detector and a post processor for generating error metrics used to correct errors made by the trellis sequence detector' [patent_app_type] => B1 [patent_app_number] => 09/307645 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 9253 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513141.pdf [firstpage_image] =>[orig_patent_app_number] => 09307645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307645
Sampled amplitude read channel employing a trellis sequence detector and a post processor for generating error metrics used to correct errors made by the trellis sequence detector May 6, 1999 Issued
Array ( [id] => 1587627 [patent_doc_number] => 06425108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Replacement of bad data bit or bad error control bit' [patent_app_type] => B1 [patent_app_number] => 09/306753 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425108.pdf [firstpage_image] =>[orig_patent_app_number] => 09306753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306753
Replacement of bad data bit or bad error control bit May 6, 1999 Issued
Array ( [id] => 1573875 [patent_doc_number] => 06499124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Intest security circuit for boundary-scan architecture' [patent_app_type] => B1 [patent_app_number] => 09/306649 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 8348 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499124.pdf [firstpage_image] =>[orig_patent_app_number] => 09306649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306649
Intest security circuit for boundary-scan architecture May 5, 1999 Issued
Array ( [id] => 1380919 [patent_doc_number] => RE038010 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Trellis encoder and decoder based upon punctured rate convolutional codes' [patent_app_type] => E1 [patent_app_number] => 09/305328 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2895 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038010.pdf [firstpage_image] =>[orig_patent_app_number] => 09305328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/305328
Trellis encoder and decoder based upon punctured rate convolutional codes May 3, 1999 Issued
Array ( [id] => 4423799 [patent_doc_number] => 06311306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'System for error control by subdividing coded information units into subsets reordering and interlacing the subsets, to produce a set of interleaved coded information units' [patent_app_type] => 1 [patent_app_number] => 9/300419 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7819 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311306.pdf [firstpage_image] =>[orig_patent_app_number] => 300419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300419
System for error control by subdividing coded information units into subsets reordering and interlacing the subsets, to produce a set of interleaved coded information units Apr 25, 1999 Issued
Array ( [id] => 1501734 [patent_doc_number] => 06405336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Device and method for testing a semiconductor' [patent_app_type] => B1 [patent_app_number] => 09/293682 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4752 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405336.pdf [firstpage_image] =>[orig_patent_app_number] => 09293682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293682
Device and method for testing a semiconductor Apr 15, 1999 Issued
Array ( [id] => 1481350 [patent_doc_number] => 06389567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Testable IC having analog and digital circuits' [patent_app_type] => B2 [patent_app_number] => 09/293925 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4121 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389567.pdf [firstpage_image] =>[orig_patent_app_number] => 09293925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293925
Testable IC having analog and digital circuits Apr 15, 1999 Issued
Array ( [id] => 1462526 [patent_doc_number] => 06427217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'System and method for scan assisted self-test of integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/292717 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5330 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427217.pdf [firstpage_image] =>[orig_patent_app_number] => 09292717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292717
System and method for scan assisted self-test of integrated circuits Apr 14, 1999 Issued
Array ( [id] => 1539422 [patent_doc_number] => 06412092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method and apparatus to reduce the cost of preparing the checksum for out bound data in network communication protocols by caching' [patent_app_type] => B1 [patent_app_number] => 09/292035 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6454 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412092.pdf [firstpage_image] =>[orig_patent_app_number] => 09292035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292035
Method and apparatus to reduce the cost of preparing the checksum for out bound data in network communication protocols by caching Apr 13, 1999 Issued
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