Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4271151 [patent_doc_number] => 06223317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Bit synchronizers and methods of synchronizing and calculating error' [patent_app_type] => 1 [patent_app_number] => 9/033065 [patent_app_country] => US [patent_app_date] => 1998-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7099 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223317.pdf [firstpage_image] =>[orig_patent_app_number] => 033065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033065
Bit synchronizers and methods of synchronizing and calculating error Feb 27, 1998 Issued
Array ( [id] => 4318675 [patent_doc_number] => 06185718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Memory card design with parity and ECC for non-parity and non-ECC systems' [patent_app_type] => 1 [patent_app_number] => 9/032195 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3070 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185718.pdf [firstpage_image] =>[orig_patent_app_number] => 032195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032195
Memory card design with parity and ECC for non-parity and non-ECC systems Feb 26, 1998 Issued
Array ( [id] => 4425009 [patent_doc_number] => 06230294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Transient analysis device for analog/digital mixed circuit and analysis method thereof' [patent_app_type] => 1 [patent_app_number] => 9/031194 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5100 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230294.pdf [firstpage_image] =>[orig_patent_app_number] => 031194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031194
Transient analysis device for analog/digital mixed circuit and analysis method thereof Feb 25, 1998 Issued
Array ( [id] => 6349211 [patent_doc_number] => 20020035713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'INFORMATION CODING METHOD AND DEVICES UTILIZING ERROR CORRECTION AND ERROR DETECTION' [patent_app_type] => new [patent_app_number] => 09/019656 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9911 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20020035713.pdf [firstpage_image] =>[orig_patent_app_number] => 09019656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019656
Information coding method and devices utilizing error correction and error detection Feb 5, 1998 Issued
Array ( [id] => 4371719 [patent_doc_number] => 06216246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism' [patent_app_type] => 1 [patent_app_number] => 8/989841 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 6554 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216246.pdf [firstpage_image] =>[orig_patent_app_number] => 989841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989841
Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism Dec 11, 1997 Issued
Array ( [id] => 4427006 [patent_doc_number] => 06195780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method and apparatus for generating cyclical redundancy code' [patent_app_type] => 1 [patent_app_number] => 8/987927 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6589 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195780.pdf [firstpage_image] =>[orig_patent_app_number] => 987927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987927
Method and apparatus for generating cyclical redundancy code Dec 9, 1997 Issued
Array ( [id] => 4240561 [patent_doc_number] => 06012157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'System for verifying the effectiveness of a RAM BIST controller\'s ability to detect faults in a RAM memory using states indicating by fault severity information' [patent_app_type] => 1 [patent_app_number] => 8/984447 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012157.pdf [firstpage_image] =>[orig_patent_app_number] => 984447 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984447
System for verifying the effectiveness of a RAM BIST controller's ability to detect faults in a RAM memory using states indicating by fault severity information Dec 2, 1997 Issued
Array ( [id] => 4382121 [patent_doc_number] => 06256764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method and system for decoding tailbiting convolution codes' [patent_app_type] => 1 [patent_app_number] => 8/979414 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3339 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256764.pdf [firstpage_image] =>[orig_patent_app_number] => 979414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979414
Method and system for decoding tailbiting convolution codes Nov 25, 1997 Issued
Array ( [id] => 4148256 [patent_doc_number] => 06128754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Tester having event generation circuit for acquiring waveform by supplying strobe events for waveform acquisition rather than using strobe events specified by the test program' [patent_app_type] => 1 [patent_app_number] => 8/977649 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5290 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128754.pdf [firstpage_image] =>[orig_patent_app_number] => 977649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977649
Tester having event generation circuit for acquiring waveform by supplying strobe events for waveform acquisition rather than using strobe events specified by the test program Nov 23, 1997 Issued
Array ( [id] => 4209810 [patent_doc_number] => 06154872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method, circuit and apparatus for preserving and/or correcting product engineering information' [patent_app_type] => 1 [patent_app_number] => 8/975343 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5355 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154872.pdf [firstpage_image] =>[orig_patent_app_number] => 975343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975343
Method, circuit and apparatus for preserving and/or correcting product engineering information Nov 19, 1997 Issued
Array ( [id] => 4058321 [patent_doc_number] => 05996107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Error correction decoder including an address generation circuit' [patent_app_type] => 1 [patent_app_number] => 8/971353 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7931 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996107.pdf [firstpage_image] =>[orig_patent_app_number] => 971353 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971353
Error correction decoder including an address generation circuit Nov 16, 1997 Issued
Array ( [id] => 4237898 [patent_doc_number] => 06112322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Circuit and method for stress testing EEPROMS' [patent_app_type] => 1 [patent_app_number] => 8/964031 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3141 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112322.pdf [firstpage_image] =>[orig_patent_app_number] => 964031 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964031
Circuit and method for stress testing EEPROMS Nov 3, 1997 Issued
Array ( [id] => 3982762 [patent_doc_number] => 05910181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core' [patent_app_type] => 1 [patent_app_number] => 8/964236 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7749 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910181.pdf [firstpage_image] =>[orig_patent_app_number] => 964236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964236
Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core Nov 3, 1997 Issued
Array ( [id] => 3837365 [patent_doc_number] => 05790889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method of selecting pointing device in a computer comprising responsive to a reconfiguration event, indentifying all connected pointing devices and selecting one of the devices' [patent_app_type] => 1 [patent_app_number] => 8/960544 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1976 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790889.pdf [firstpage_image] =>[orig_patent_app_number] => 960544 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960544
Method of selecting pointing device in a computer comprising responsive to a reconfiguration event, indentifying all connected pointing devices and selecting one of the devices Oct 30, 1997 Issued
Array ( [id] => 4240533 [patent_doc_number] => 06012155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method and system for performing automatic extraction and compliance checking of an IEEE 1149.1 standard design within a netlist' [patent_app_type] => 1 [patent_app_number] => 8/961389 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 36 [patent_no_of_words] => 13047 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012155.pdf [firstpage_image] =>[orig_patent_app_number] => 961389 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961389
Method and system for performing automatic extraction and compliance checking of an IEEE 1149.1 standard design within a netlist Oct 29, 1997 Issued
Array ( [id] => 3983827 [patent_doc_number] => 05887141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Systems for work assignment and distribution from a server to remote/mobile nodes by a hierarchy of session work objects into which events can be assigned' [patent_app_type] => 1 [patent_app_number] => 8/953330 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5744 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887141.pdf [firstpage_image] =>[orig_patent_app_number] => 953330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953330
Systems for work assignment and distribution from a server to remote/mobile nodes by a hierarchy of session work objects into which events can be assigned Oct 16, 1997 Issued
Array ( [id] => 3971697 [patent_doc_number] => 06000052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Signal conditioning system for controlling data retrieval channel characteristics in which errors in samples are segregated by association with intended sample values to control selected characteristics' [patent_app_type] => 1 [patent_app_number] => 8/930972 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8731 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 482 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000052.pdf [firstpage_image] =>[orig_patent_app_number] => 930972 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/930972
Signal conditioning system for controlling data retrieval channel characteristics in which errors in samples are segregated by association with intended sample values to control selected characteristics Oct 6, 1997 Issued
08/946470 SYSTEM FOR FINDING ROOTS OF DEGREE THREE AND DEGREE FOUR ERROR LOCATOR POLYNOMIALS OVER GF(2M) Oct 6, 1997 Abandoned
Array ( [id] => 4216090 [patent_doc_number] => 06014761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Convolutional interleaving/de-interleaving method using pointer incrementing across predetermined distances and apparatus for data transmission' [patent_app_type] => 1 [patent_app_number] => 8/944699 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014761.pdf [firstpage_image] =>[orig_patent_app_number] => 944699 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944699
Convolutional interleaving/de-interleaving method using pointer incrementing across predetermined distances and apparatus for data transmission Oct 5, 1997 Issued
Array ( [id] => 4178606 [patent_doc_number] => 06108811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Error-correcting decoder continuously adding flag signals to locations preceding a first location at which a difference between path metrics is lower than the threshold' [patent_app_type] => 1 [patent_app_number] => 8/944292 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 5683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108811.pdf [firstpage_image] =>[orig_patent_app_number] => 944292 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944292
Error-correcting decoder continuously adding flag signals to locations preceding a first location at which a difference between path metrics is lower than the threshold Oct 5, 1997 Issued
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