| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_issue_date] => 1998-06-23
[patent_title] => 'System for processing information from scanned documents using event driven interface with patterns loaded in RAM and with address generator for addressing bit patterns'
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[patent_app_number] => 8/635842
[patent_app_country] => US
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Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'System for physical storage architecture providing simultaneous access to common file by storing update data in update partitions and merging desired updates into common partition'
[patent_app_type] => 1
[patent_app_number] => 8/633839
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[firstpage_image] =>[orig_patent_app_number] => 633839
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/633839 | System for physical storage architecture providing simultaneous access to common file by storing update data in update partitions and merging desired updates into common partition | Apr 9, 1996 | Issued |
Array
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[id] => 3795165
[patent_doc_number] => 05809333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status'
[patent_app_type] => 1
[patent_app_number] => 8/627988
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Array
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[patent_doc_number] => 05905912
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
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[patent_app_type] => 1
[patent_app_number] => 8/627989
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Array
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[patent_kind] => NA
[patent_issue_date] => 1998-06-30
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Array
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[patent_kind] => NA
[patent_issue_date] => 1998-08-25
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Array
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[id] => 3768550
[patent_doc_number] => 05721953
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[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready'
[patent_app_type] => 1
[patent_app_number] => 8/626101
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[firstpage_image] =>[orig_patent_app_number] => 626101
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Array
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[patent_doc_number] => 05799211
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Shift register having latch cell operable in serial-in/parallel-out and parallel-in/serial-out modes in response to a sequence of commands for controlling appropriate switches'
[patent_app_type] => 1
[patent_app_number] => 8/621020
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Array
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[patent_issue_date] => 1998-06-16
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Array
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[patent_issue_date] => 1999-01-19
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Array
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[patent_issue_date] => 1999-07-13
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Array
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[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/881/05881310.pdf
[firstpage_image] =>[orig_patent_app_number] => 589834
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/589834 | Method for executing an instruction where the memory locations for data, operation to be performed and storing of the result are indicated by pointers | Jan 21, 1996 | Issued |