Search

David Ton

Examiner (ID: 2768, Phone: (571)272-3828 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2782, 2117, 2784, 2317, 2133, 2138
Total Applications
1397
Issued Applications
1295
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3829202 [patent_doc_number] => 05771395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'System for processing information from scanned documents using event driven interface with patterns loaded in RAM and with address generator for addressing bit patterns' [patent_app_type] => 1 [patent_app_number] => 8/635842 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3408 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771395.pdf [firstpage_image] =>[orig_patent_app_number] => 635842 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/635842
System for processing information from scanned documents using event driven interface with patterns loaded in RAM and with address generator for addressing bit patterns Apr 21, 1996 Issued
Array ( [id] => 3782521 [patent_doc_number] => 05850522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'System for physical storage architecture providing simultaneous access to common file by storing update data in update partitions and merging desired updates into common partition' [patent_app_type] => 1 [patent_app_number] => 8/633839 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8094 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850522.pdf [firstpage_image] =>[orig_patent_app_number] => 633839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/633839
System for physical storage architecture providing simultaneous access to common file by storing update data in update partitions and merging desired updates into common partition Apr 9, 1996 Issued
Array ( [id] => 3795165 [patent_doc_number] => 05809333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status' [patent_app_type] => 1 [patent_app_number] => 8/627988 [patent_app_country] => US [patent_app_date] => 1996-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809333.pdf [firstpage_image] =>[orig_patent_app_number] => 627988 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627988
System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status Apr 7, 1996 Issued
Array ( [id] => 3989998 [patent_doc_number] => 05905912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receiving control signals external to the DMA controller' [patent_app_type] => 1 [patent_app_number] => 8/627989 [patent_app_country] => US [patent_app_date] => 1996-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 3669 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905912.pdf [firstpage_image] =>[orig_patent_app_number] => 627989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627989
System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receiving control signals external to the DMA controller Apr 7, 1996 Issued
Array ( [id] => 3788904 [patent_doc_number] => 05774743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'System for implementing peripheral device bus mastering in mobile computer via micro-controller for programming DMA controller, generating and sending command signals, and receiving completion status' [patent_app_type] => 1 [patent_app_number] => 8/627987 [patent_app_country] => US [patent_app_date] => 1996-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774743.pdf [firstpage_image] =>[orig_patent_app_number] => 627987 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627987
System for implementing peripheral device bus mastering in mobile computer via micro-controller for programming DMA controller, generating and sending command signals, and receiving completion status Apr 7, 1996 Issued
Array ( [id] => 3895291 [patent_doc_number] => 05799208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Apparatus for data communication between universal asynchronous receiver/transmitter (UART) modules and transceivers in a chip set by selectively connecting a common bus between multiplexer/demultiplexer units' [patent_app_type] => 1 [patent_app_number] => 8/626947 [patent_app_country] => US [patent_app_date] => 1996-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1997 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799208.pdf [firstpage_image] =>[orig_patent_app_number] => 626947 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626947
Apparatus for data communication between universal asynchronous receiver/transmitter (UART) modules and transceivers in a chip set by selectively connecting a common bus between multiplexer/demultiplexer units Apr 2, 1996 Issued
Array ( [id] => 3768550 [patent_doc_number] => 05721953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready' [patent_app_type] => 1 [patent_app_number] => 8/626101 [patent_app_country] => US [patent_app_date] => 1996-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 10280 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721953.pdf [firstpage_image] =>[orig_patent_app_number] => 626101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626101
Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready Apr 2, 1996 Issued
Array ( [id] => 3895347 [patent_doc_number] => 05799211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Shift register having latch cell operable in serial-in/parallel-out and parallel-in/serial-out modes in response to a sequence of commands for controlling appropriate switches' [patent_app_type] => 1 [patent_app_number] => 8/621020 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2685 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799211.pdf [firstpage_image] =>[orig_patent_app_number] => 621020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621020
Shift register having latch cell operable in serial-in/parallel-out and parallel-in/serial-out modes in response to a sequence of commands for controlling appropriate switches Mar 21, 1996 Issued
Array ( [id] => 3873468 [patent_doc_number] => 05768632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Method for operating inductrial control with control program and I/O map by transmitting function key to particular module for comparison with function code before operating' [patent_app_type] => 1 [patent_app_number] => 8/620963 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5031 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768632.pdf [firstpage_image] =>[orig_patent_app_number] => 620963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620963
Method for operating inductrial control with control program and I/O map by transmitting function key to particular module for comparison with function code before operating Mar 21, 1996 Issued
Array ( [id] => 3998722 [patent_doc_number] => 05862402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'System for rapidly issuing IC cards by proving an association between stored issue data and discrimination data then issuing IC cards pursuant to the issue data' [patent_app_type] => 1 [patent_app_number] => 8/619321 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3259 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862402.pdf [firstpage_image] =>[orig_patent_app_number] => 619321 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619321
System for rapidly issuing IC cards by proving an association between stored issue data and discrimination data then issuing IC cards pursuant to the issue data Mar 20, 1996 Issued
Array ( [id] => 4015131 [patent_doc_number] => 05923896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method for sequencing execution of I/O command blocks in a chain structure by setting hold-off flags and configuring a counter in each I/O command block' [patent_app_type] => 1 [patent_app_number] => 8/617990 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 27013 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923896.pdf [firstpage_image] =>[orig_patent_app_number] => 617990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617990
Method for sequencing execution of I/O command blocks in a chain structure by setting hold-off flags and configuring a counter in each I/O command block Mar 14, 1996 Issued
Array ( [id] => 3797448 [patent_doc_number] => 05819111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'System for managing transfer of data by delaying flow controlling of data through the interface controller until the run length encoded data transfer is complete' [patent_app_type] => 1 [patent_app_number] => 8/619819 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6333 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819111.pdf [firstpage_image] =>[orig_patent_app_number] => 619819 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619819
System for managing transfer of data by delaying flow controlling of data through the interface controller until the run length encoded data transfer is complete Mar 14, 1996 Issued
Array ( [id] => 4070967 [patent_doc_number] => 05864738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller' [patent_app_type] => 1 [patent_app_number] => 8/614859 [patent_app_country] => US [patent_app_date] => 1996-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11588 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864738.pdf [firstpage_image] =>[orig_patent_app_number] => 614859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/614859
Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller Mar 12, 1996 Issued
Array ( [id] => 3858093 [patent_doc_number] => 05848296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method for starting up recording and reproducing apparatus by allowing the host computer to receive necessary programs from recording and reproducing apparatus ilustratively upon power-up' [patent_app_type] => 1 [patent_app_number] => 8/616400 [patent_app_country] => US [patent_app_date] => 1996-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1975 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848296.pdf [firstpage_image] =>[orig_patent_app_number] => 616400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616400
Method for starting up recording and reproducing apparatus by allowing the host computer to receive necessary programs from recording and reproducing apparatus ilustratively upon power-up Mar 12, 1996 Issued
Array ( [id] => 3910868 [patent_doc_number] => 05835784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'System for booting processor from remote memory by preventing host processor from configuring an environment of processor while configuring an interface unit between processor and remote memory' [patent_app_type] => 1 [patent_app_number] => 8/611802 [patent_app_country] => US [patent_app_date] => 1996-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3348 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835784.pdf [firstpage_image] =>[orig_patent_app_number] => 611802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611802
System for booting processor from remote memory by preventing host processor from configuring an environment of processor while configuring an interface unit between processor and remote memory Mar 5, 1996 Issued
Array ( [id] => 3793887 [patent_doc_number] => 05809249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'System having at least one auto-negotiation enabled physical media dependent (PMD) interface device operable to perform auto-negotiation with remote link partner on behalf of all PMD' [patent_app_type] => 1 [patent_app_number] => 8/609575 [patent_app_country] => US [patent_app_date] => 1996-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2752 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809249.pdf [firstpage_image] =>[orig_patent_app_number] => 609575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/609575
System having at least one auto-negotiation enabled physical media dependent (PMD) interface device operable to perform auto-negotiation with remote link partner on behalf of all PMD Feb 29, 1996 Issued
Array ( [id] => 3850420 [patent_doc_number] => 05761518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'System for replacing control processor by operating processor in partially disabled mode for tracking control outputs and in write enabled mode for transferring control loops' [patent_app_type] => 1 [patent_app_number] => 8/609063 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761518.pdf [firstpage_image] =>[orig_patent_app_number] => 609063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/609063
System for replacing control processor by operating processor in partially disabled mode for tracking control outputs and in write enabled mode for transferring control loops Feb 28, 1996 Issued
Array ( [id] => 3905562 [patent_doc_number] => 05778257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Multi-session disc-shaped for recording audio and computer data having disc type code area located in each session for recording common and particular disc type code' [patent_app_type] => 1 [patent_app_number] => 8/592962 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7232 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778257.pdf [firstpage_image] =>[orig_patent_app_number] => 592962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592962
Multi-session disc-shaped for recording audio and computer data having disc type code area located in each session for recording common and particular disc type code Jan 28, 1996 Issued
Array ( [id] => 4166517 [patent_doc_number] => 06065047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'System for providing subscriber with access to a content area customized for the combination of subscriber\'s responses to topic prompt, subtopic prompt, and action prompt' [patent_app_type] => 1 [patent_app_number] => 8/590929 [patent_app_country] => US [patent_app_date] => 1996-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4860 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065047.pdf [firstpage_image] =>[orig_patent_app_number] => 590929 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590929
System for providing subscriber with access to a content area customized for the combination of subscriber's responses to topic prompt, subtopic prompt, and action prompt Jan 23, 1996 Issued
Array ( [id] => 4031953 [patent_doc_number] => 05881310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method for executing an instruction where the memory locations for data, operation to be performed and storing of the result are indicated by pointers' [patent_app_type] => 1 [patent_app_number] => 8/589834 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 30521 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881310.pdf [firstpage_image] =>[orig_patent_app_number] => 589834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/589834
Method for executing an instruction where the memory locations for data, operation to be performed and storing of the result are indicated by pointers Jan 21, 1996 Issued
Menu