Search

David Ton

Examiner (ID: 9677)

Most Active Art Unit
2117
Art Unit(s)
2317, 2138, 2782, 2784, 2133, 2117
Total Applications
1397
Issued Applications
1294
Pending Applications
31
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9807987 [patent_doc_number] => 20150019932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'STORAGE DEVICE, CRC GENERATION DEVICE, AND CRC GENERATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/018676 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6319 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018676 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018676
Storage device, CRC generation device, and CRC generation method Sep 4, 2013 Issued
Array ( [id] => 9999054 [patent_doc_number] => 09043672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Memory controller, storage device, and memory control method' [patent_app_type] => utility [patent_app_number] => 14/017809 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4711 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017809 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017809
Memory controller, storage device, and memory control method Sep 3, 2013 Issued
Array ( [id] => 9599193 [patent_doc_number] => 20140195874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/017259 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017259 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017259
Memory system Sep 2, 2013 Issued
Array ( [id] => 9912233 [patent_doc_number] => 20150067436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'Nonvolatile Memory System Compression' [patent_app_type] => utility [patent_app_number] => 14/016954 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6522 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016954 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016954
Nonvolatile Memory System Compression Sep 2, 2013 Abandoned
Array ( [id] => 10337388 [patent_doc_number] => 20150222393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'METHOD FOR PROVIDING AUTOMATIC REPEAT REQUEST ERROR CONTROL AND RELATED TERMINAL AND ARQ CONTROL CENTER' [patent_app_type] => utility [patent_app_number] => 14/421990 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5886 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14421990 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/421990
METHOD FOR PROVIDING AUTOMATIC REPEAT REQUEST ERROR CONTROL AND RELATED TERMINAL AND ARQ CONTROL CENTER Sep 2, 2013 Abandoned
Array ( [id] => 9912216 [patent_doc_number] => 20150067419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'Bad Block Reconfiguration in Nonvolatile Memory' [patent_app_type] => utility [patent_app_number] => 14/016785 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9736 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016785 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016785
Bad block reconfiguration in nonvolatile memory Sep 2, 2013 Issued
Array ( [id] => 9912226 [patent_doc_number] => 20150067429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'WAFER-LEVEL GATE STRESS TESTING' [patent_app_type] => utility [patent_app_number] => 14/016957 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016957 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016957
Wafer-level gate stress testing Sep 2, 2013 Issued
Array ( [id] => 9912213 [patent_doc_number] => 20150067417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'METHOD FOR TESTING DATA PACKET SIGNAL TRANSCEIVERS WITH MULTIPLE RADIO ACCESS TECHNOLOGIES USING INTERLEAVED DEVICE SETUP AND TESTING' [patent_app_type] => utility [patent_app_number] => 14/017077 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4938 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017077 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017077
Method for testing data packet signal transceivers with multiple radio access technologies using interleaved device setup and testing Sep 2, 2013 Issued
Array ( [id] => 9465474 [patent_doc_number] => 20140129901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/017246 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017246 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017246
Memory system Sep 2, 2013 Issued
Array ( [id] => 9332624 [patent_doc_number] => 20140059406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'REDUCED LEVEL CELL MODE FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/016203 [patent_app_country] => US [patent_app_date] => 2013-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 37383 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016203 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016203
Reduced level cell mode for non-volatile memory Sep 1, 2013 Issued
Array ( [id] => 10078978 [patent_doc_number] => 09116827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'System and method for optimizing luby transform (LT) codes to facilitate data transmission over communication network' [patent_app_type] => utility [patent_app_number] => 14/015034 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5023 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14015034 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/015034
System and method for optimizing luby transform (LT) codes to facilitate data transmission over communication network Aug 29, 2013 Issued
Array ( [id] => 9912288 [patent_doc_number] => 20150067490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'VIRTUAL INTERFACE ADJUSTMENT METHODS AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/015771 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14015771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/015771
Virtual interface adjustment methods and systems Aug 29, 2013 Issued
Array ( [id] => 9912221 [patent_doc_number] => 20150067424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'PROCESSOR TAP SUPPORT FOR REMOTE SERVICES' [patent_app_type] => utility [patent_app_number] => 14/014155 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14014155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/014155
Processor TAP support for remote services Aug 28, 2013 Issued
Array ( [id] => 9341580 [patent_doc_number] => 20140068364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'MODIFIED CONDITION/DECISION COVERAGE TEST CASE AUTOMATION' [patent_app_type] => utility [patent_app_number] => 14/013583 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2375 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013583 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/013583
Modified condition/decision coverage test case automation Aug 28, 2013 Issued
Array ( [id] => 9912228 [patent_doc_number] => 20150067431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'DATA RECOVERY OF DATA SYMBOLS RECEIVED IN ERROR' [patent_app_type] => utility [patent_app_number] => 14/012492 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14012492 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/012492
Data recovery of data symbols received in error Aug 27, 2013 Issued
Array ( [id] => 9912220 [patent_doc_number] => 20150067423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS) TESTING AND AN ALGORITHM TO IDENTIFY BEST Q-GATING CANDIDATES' [patent_app_type] => utility [patent_app_number] => 14/011786 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14011786 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/011786
Q-gating cell architecture to satiate the launch-off-shift (LOS) testing and an algorithm to identify best Q-gating candidates Aug 27, 2013 Issued
Array ( [id] => 10014749 [patent_doc_number] => 09057762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'Faulty chains identification without masking chain patterns' [patent_app_type] => utility [patent_app_number] => 14/011995 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3955 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14011995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/011995
Faulty chains identification without masking chain patterns Aug 27, 2013 Issued
Array ( [id] => 10111388 [patent_doc_number] => 09146804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Apparatus and method for detecting bit sequence robustly to change of DC offset in OOK receiver' [patent_app_type] => utility [patent_app_number] => 14/012016 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10869 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14012016 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/012016
Apparatus and method for detecting bit sequence robustly to change of DC offset in OOK receiver Aug 27, 2013 Issued
Array ( [id] => 9341576 [patent_doc_number] => 20140068360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SYSTEMS AND METHODS FOR TESTING MEMORY' [patent_app_type] => utility [patent_app_number] => 14/011508 [patent_app_country] => US [patent_app_date] => 2013-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12935 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14011508 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/011508
Systems and methods for testing memory Aug 26, 2013 Issued
Array ( [id] => 9507126 [patent_doc_number] => 08745456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Controlling user-added boundary scan register with TAP of IP core' [patent_app_type] => utility [patent_app_number] => 13/969079 [patent_app_country] => US [patent_app_date] => 2013-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3660 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969079 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/969079
Controlling user-added boundary scan register with TAP of IP core Aug 15, 2013 Issued
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