David Vu

Array ( [id] => 4259406 [patent_doc_number] => 06258705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip' [patent_app_type] => 1 [patent_app_number] => 9/642319 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3321 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258705.pdf [firstpage_image] =>[orig_patent_app_number] => 642319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1050096 [patent_doc_number] => 06861375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/640519 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5526 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861375.pdf [firstpage_image] =>[orig_patent_app_number] => 09640519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561211 [patent_doc_number] => 06362094 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Hydrogenated silicon carbide as a liner for self-aligning contact vias' [patent_app_type] => B1 [patent_app_number] => 09/640329 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2544 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362094.pdf [firstpage_image] =>[orig_patent_app_number] => 09640329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4343533 [patent_doc_number] => 06284572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Boat and assembly method for ball grid array packages' [patent_app_type] => 1 [patent_app_number] => 9/638749 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1925 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284572.pdf [firstpage_image] =>[orig_patent_app_number] => 638749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1399718 [patent_doc_number] => 06537926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Process for improving the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication' [patent_app_type] => B1 [patent_app_number] => 09/638309 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5537 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537926.pdf [firstpage_image] =>[orig_patent_app_number] => 09638309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269758 [patent_doc_number] => 06245621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/637579 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 4560 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245621.pdf [firstpage_image] =>[orig_patent_app_number] => 637579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561181 [patent_doc_number] => 06362084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method of manufacturing a substrate for displays and a substrate for displays manufactured by same' [patent_app_type] => B1 [patent_app_number] => 09/619329 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5649 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362084.pdf [firstpage_image] =>[orig_patent_app_number] => 09619329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1231403 [patent_doc_number] => 06693030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Reactive preclean prior to metallization for sub-quarter micron application' [patent_app_type] => B1 [patent_app_number] => 09/617522 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6328 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693030.pdf [firstpage_image] =>[orig_patent_app_number] => 09617522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1559626 [patent_doc_number] => 06436740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Tri-layer process for forming TFT matrix of LCD with reduced masking steps' [patent_app_type] => B1 [patent_app_number] => 09/615919 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 43 [patent_no_of_words] => 5294 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436740.pdf [firstpage_image] =>[orig_patent_app_number] => 09615919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365787 [patent_doc_number] => 06274418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method of manufacturing flash memory cell' [patent_app_type] => 1 [patent_app_number] => 9/609159 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1138 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274418.pdf [firstpage_image] =>[orig_patent_app_number] => 609159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466955 [patent_doc_number] => 06458646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Asymmetric gates for high density DRAM' [patent_app_type] => B1 [patent_app_number] => 09/608019 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4358 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458646.pdf [firstpage_image] =>[orig_patent_app_number] => 09608019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1409767 [patent_doc_number] => 06528399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'MOSFET transistor with short channel effect compensated by the gate material' [patent_app_type] => B1 [patent_app_number] => 09/606600 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3405 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528399.pdf [firstpage_image] =>[orig_patent_app_number] => 09606600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4382044 [patent_doc_number] => 06294484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method of forming TEOS oxide films' [patent_app_type] => 1 [patent_app_number] => 9/605659 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2002 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294484.pdf [firstpage_image] =>[orig_patent_app_number] => 605659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350952 [patent_doc_number] => 06291338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method of fabricating self-aligned polysilicon via plug' [patent_app_type] => 1 [patent_app_number] => 9/605089 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2367 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291338.pdf [firstpage_image] =>[orig_patent_app_number] => 605089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1578055 [patent_doc_number] => 06448122 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method and device structure for enhanced ESD performance' [patent_app_type] => B1 [patent_app_number] => 09/598759 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2485 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448122.pdf [firstpage_image] =>[orig_patent_app_number] => 09598759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1469713 [patent_doc_number] => 06406929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Structure and method for abrupt PN junction diode formed using chemical vapor deposition processing' [patent_app_type] => B1 [patent_app_number] => 09/598529 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6644 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406929.pdf [firstpage_image] =>[orig_patent_app_number] => 09598529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381127 [patent_doc_number] => 06261904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Dual bit isolation scheme for flash devices' [patent_app_type] => 1 [patent_app_number] => 9/596449 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 4544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261904.pdf [firstpage_image] =>[orig_patent_app_number] => 596449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1414952 [patent_doc_number] => 06521542 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method for forming dual damascene structure' [patent_app_type] => B1 [patent_app_number] => 09/593739 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521542.pdf [firstpage_image] =>[orig_patent_app_number] => 09593739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 446027 [patent_doc_number] => 07253076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-07 [patent_title] => 'Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers' [patent_app_type] => utility [patent_app_number] => 09/590795 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4998 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253076.pdf [firstpage_image] =>[orig_patent_app_number] => 09590795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7636635 [patent_doc_number] => 06380020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method for fabricating a semiconductor device having a device isolation insulating film' [patent_app_type] => B1 [patent_app_number] => 09/589729 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6468 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380020.pdf [firstpage_image] =>[orig_patent_app_number] => 09589729 [rel_patent_id] =>[rel_patent_doc_number] =>)