
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4343939
[patent_doc_number] => 06284599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Method to fabricate a semiconductor resistor in embedded flash memory application'
[patent_app_type] => 1
[patent_app_number] => 9/585059
[patent_app_country] => US
[patent_app_date] => 2000-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 4838
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/284/06284599.pdf
[firstpage_image] =>[orig_patent_app_number] => 585059
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/585059 | Method to fabricate a semiconductor resistor in embedded flash memory application | May 31, 2000 | Issued |
Array
(
[id] => 1462602
[patent_doc_number] => 06350680
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Pad alignment for AlCu pad for copper process'
[patent_app_type] => B1
[patent_app_number] => 09/578409
[patent_app_country] => US
[patent_app_date] => 2000-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2871
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350680.pdf
[firstpage_image] =>[orig_patent_app_number] => 09578409
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/578409 | Pad alignment for AlCu pad for copper process | May 25, 2000 | Issued |
Array
(
[id] => 4407988
[patent_doc_number] => 06309917
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Thin film transistor manufacturing method and thin film transistor'
[patent_app_type] => 1
[patent_app_number] => 9/566609
[patent_app_country] => US
[patent_app_date] => 2000-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3487
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/309/06309917.pdf
[firstpage_image] =>[orig_patent_app_number] => 566609
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/566609 | Thin film transistor manufacturing method and thin film transistor | May 8, 2000 | Issued |
Array
(
[id] => 1459311
[patent_doc_number] => 06391701
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Semiconductor device and process of fabrication thereof'
[patent_app_type] => B1
[patent_app_number] => 09/566074
[patent_app_country] => US
[patent_app_date] => 2000-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 23
[patent_no_of_words] => 6426
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/391/06391701.pdf
[firstpage_image] =>[orig_patent_app_number] => 09566074
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/566074 | Semiconductor device and process of fabrication thereof | May 7, 2000 | Issued |
Array
(
[id] => 4380990
[patent_doc_number] => 06294414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Method of fabricating heterointerface devices having diffused junctions'
[patent_app_type] => 1
[patent_app_number] => 9/564769
[patent_app_country] => US
[patent_app_date] => 2000-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2625
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/294/06294414.pdf
[firstpage_image] =>[orig_patent_app_number] => 564769
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/564769 | Method of fabricating heterointerface devices having diffused junctions | May 3, 2000 | Issued |
Array
(
[id] => 1459884
[patent_doc_number] => 06426534
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-30
[patent_title] => 'Methods and circuits employing threshold voltages for mask-alignment detection'
[patent_app_type] => B1
[patent_app_number] => 09/561785
[patent_app_country] => US
[patent_app_date] => 2000-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 5144
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/426/06426534.pdf
[firstpage_image] =>[orig_patent_app_number] => 09561785
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/561785 | Methods and circuits employing threshold voltages for mask-alignment detection | Apr 30, 2000 | Issued |
Array
(
[id] => 1537164
[patent_doc_number] => 06337503
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-08
[patent_title] => 'Integrated power circuit with reduced parasitic current flow'
[patent_app_type] => B1
[patent_app_number] => 09/560195
[patent_app_country] => US
[patent_app_date] => 2000-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3430
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/337/06337503.pdf
[firstpage_image] =>[orig_patent_app_number] => 09560195
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/560195 | Integrated power circuit with reduced parasitic current flow | Apr 27, 2000 | Issued |
Array
(
[id] => 1433546
[patent_doc_number] => 06340836
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Semiconductor device for rectifying'
[patent_app_type] => B1
[patent_app_number] => 09/559470
[patent_app_country] => US
[patent_app_date] => 2000-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 5782
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/340/06340836.pdf
[firstpage_image] =>[orig_patent_app_number] => 09559470
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/559470 | Semiconductor device for rectifying | Apr 25, 2000 | Issued |
Array
(
[id] => 1565678
[patent_doc_number] => 06376291
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Process for manufacturing buried channels and cavities in semiconductor material wafers'
[patent_app_type] => B1
[patent_app_number] => 09/558959
[patent_app_country] => US
[patent_app_date] => 2000-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 1952
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/376/06376291.pdf
[firstpage_image] =>[orig_patent_app_number] => 09558959
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/558959 | Process for manufacturing buried channels and cavities in semiconductor material wafers | Apr 24, 2000 | Issued |
Array
(
[id] => 1136534
[patent_doc_number] => 06784518
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-31
[patent_title] => 'Integrated circuit device comprising an inductor with high quality coefficient'
[patent_app_type] => B1
[patent_app_number] => 09/553916
[patent_app_country] => US
[patent_app_date] => 2000-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4352
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/784/06784518.pdf
[firstpage_image] =>[orig_patent_app_number] => 09553916
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/553916 | Integrated circuit device comprising an inductor with high quality coefficient | Apr 19, 2000 | Issued |
Array
(
[id] => 1404187
[patent_doc_number] => 06531747
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/553334
[patent_app_country] => US
[patent_app_date] => 2000-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 7729
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/531/06531747.pdf
[firstpage_image] =>[orig_patent_app_number] => 09553334
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/553334 | Semiconductor device | Apr 19, 2000 | Issued |
Array
(
[id] => 1542495
[patent_doc_number] => 06372557
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Method of manufacturing a lateral fet having source contact to substrate with low resistance'
[patent_app_type] => B1
[patent_app_number] => 09/552239
[patent_app_country] => US
[patent_app_date] => 2000-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 2764
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/372/06372557.pdf
[firstpage_image] =>[orig_patent_app_number] => 09552239
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/552239 | Method of manufacturing a lateral fet having source contact to substrate with low resistance | Apr 18, 2000 | Issued |
Array
(
[id] => 4270640
[patent_doc_number] => 06323059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Method of fabricating a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/550209
[patent_app_country] => US
[patent_app_date] => 2000-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 20762
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/323/06323059.pdf
[firstpage_image] =>[orig_patent_app_number] => 550209
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/550209 | Method of fabricating a semiconductor device | Apr 16, 2000 | Issued |
Array
(
[id] => 1059465
[patent_doc_number] => 06852555
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-08
[patent_title] => 'Method in the fabrication of organic thin-film semiconducting devices'
[patent_app_type] => utility
[patent_app_number] => 09/720329
[patent_app_country] => US
[patent_app_date] => 2000-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6022
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/852/06852555.pdf
[firstpage_image] =>[orig_patent_app_number] => 09720329
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/720329 | Method in the fabrication of organic thin-film semiconducting devices | Apr 13, 2000 | Issued |
Array
(
[id] => 1571150
[patent_doc_number] => 06498369
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-24
[patent_title] => 'Electro-optical device and electronic equipment'
[patent_app_type] => B1
[patent_app_number] => 09/547736
[patent_app_country] => US
[patent_app_date] => 2000-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 59
[patent_no_of_words] => 22950
[patent_no_of_claims] => 95
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/498/06498369.pdf
[firstpage_image] =>[orig_patent_app_number] => 09547736
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/547736 | Electro-optical device and electronic equipment | Apr 10, 2000 | Issued |
Array
(
[id] => 1490296
[patent_doc_number] => 06417092
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Low dielectric constant etch stop films'
[patent_app_type] => B1
[patent_app_number] => 09/543149
[patent_app_country] => US
[patent_app_date] => 2000-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 3021
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/417/06417092.pdf
[firstpage_image] =>[orig_patent_app_number] => 09543149
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/543149 | Low dielectric constant etch stop films | Apr 4, 2000 | Issued |
Array
(
[id] => 7643912
[patent_doc_number] => 06429126
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Reduced fluorine contamination for tungsten CVD'
[patent_app_type] => B1
[patent_app_number] => 09/538379
[patent_app_country] => US
[patent_app_date] => 2000-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 6655
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429126.pdf
[firstpage_image] =>[orig_patent_app_number] => 09538379
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/538379 | Reduced fluorine contamination for tungsten CVD | Mar 28, 2000 | Issued |
Array
(
[id] => 4310515
[patent_doc_number] => 06316336
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Method for forming buried layers with top-side contacts and the resulting structure'
[patent_app_type] => 1
[patent_app_number] => 9/516009
[patent_app_country] => US
[patent_app_date] => 2000-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 2483
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/316/06316336.pdf
[firstpage_image] =>[orig_patent_app_number] => 516009
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/516009 | Method for forming buried layers with top-side contacts and the resulting structure | Feb 28, 2000 | Issued |
Array
(
[id] => 4271452
[patent_doc_number] => 06323112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Method of fabricating integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/498329
[patent_app_country] => US
[patent_app_date] => 2000-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3677
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/323/06323112.pdf
[firstpage_image] =>[orig_patent_app_number] => 498329
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/498329 | Method of fabricating integrated circuits | Feb 3, 2000 | Issued |
Array
(
[id] => 4380768
[patent_doc_number] => 06294399
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Quantum thin line producing method and semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/492329
[patent_app_country] => US
[patent_app_date] => 2000-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 43
[patent_no_of_words] => 9328
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/294/06294399.pdf
[firstpage_image] =>[orig_patent_app_number] => 492329
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/492329 | Quantum thin line producing method and semiconductor device | Jan 26, 2000 | Issued |