Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1566049 [patent_doc_number] => 06376370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy' [patent_app_type] => B1 [patent_app_number] => 09/484002 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 16317 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376370.pdf [firstpage_image] =>[orig_patent_app_number] => 09484002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484002
Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy Jan 17, 2000 Issued
Array ( [id] => 7636549 [patent_doc_number] => 06380108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby' [patent_app_type] => B1 [patent_app_number] => 09/468995 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4565 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380108.pdf [firstpage_image] =>[orig_patent_app_number] => 09468995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468995
Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby Dec 20, 1999 Issued
Array ( [id] => 1092832 [patent_doc_number] => 06825087 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Hydrogen anneal for creating an enhanced trench for trench MOSFETS' [patent_app_type] => B1 [patent_app_number] => 09/448884 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3151 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825087.pdf [firstpage_image] =>[orig_patent_app_number] => 09448884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448884
Hydrogen anneal for creating an enhanced trench for trench MOSFETS Nov 23, 1999 Issued
Array ( [id] => 4249496 [patent_doc_number] => 06207487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method for forming dielectric film of capacitor having different thicknesses partly' [patent_app_type] => 1 [patent_app_number] => 9/415830 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5031 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207487.pdf [firstpage_image] =>[orig_patent_app_number] => 415830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415830
Method for forming dielectric film of capacitor having different thicknesses partly Oct 11, 1999 Issued
Array ( [id] => 4368793 [patent_doc_number] => 06287923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method of forming a MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/414900 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 2294 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287923.pdf [firstpage_image] =>[orig_patent_app_number] => 414900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414900
Method of forming a MOS transistor Oct 7, 1999 Issued
Array ( [id] => 4377236 [patent_doc_number] => 06303416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method to reduce plasma etch fluting' [patent_app_type] => 1 [patent_app_number] => 9/414457 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3908 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303416.pdf [firstpage_image] =>[orig_patent_app_number] => 414457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414457
Method to reduce plasma etch fluting Oct 6, 1999 Issued
Array ( [id] => 4286560 [patent_doc_number] => 06268243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method for fabricating dynamic random access memory cells' [patent_app_type] => 1 [patent_app_number] => 9/413037 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 4591 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268243.pdf [firstpage_image] =>[orig_patent_app_number] => 413037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413037
Method for fabricating dynamic random access memory cells Oct 5, 1999 Issued
Array ( [id] => 4408103 [patent_doc_number] => 06265257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence' [patent_app_type] => 1 [patent_app_number] => 9/409877 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3440 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265257.pdf [firstpage_image] =>[orig_patent_app_number] => 409877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409877
Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence Sep 30, 1999 Issued
Array ( [id] => 4395014 [patent_doc_number] => 06297122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method of forming conductive film and capacitor' [patent_app_type] => 1 [patent_app_number] => 9/408837 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 10368 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297122.pdf [firstpage_image] =>[orig_patent_app_number] => 408837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408837
Method of forming conductive film and capacitor Sep 29, 1999 Issued
Array ( [id] => 5968490 [patent_doc_number] => 20020090769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'LIQUID CRYSTAL DEVICE, LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => new [patent_app_number] => 09/409266 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5684 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20020090769.pdf [firstpage_image] =>[orig_patent_app_number] => 09409266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409266
Liquid crystal device, liquid crystal display panel and method for manufacturing the same Sep 29, 1999 Issued
Array ( [id] => 4378792 [patent_doc_number] => 06303518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers' [patent_app_type] => 1 [patent_app_number] => 9/409580 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6238 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303518.pdf [firstpage_image] =>[orig_patent_app_number] => 409580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409580
Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers Sep 29, 1999 Issued
Array ( [id] => 1549836 [patent_doc_number] => 06346476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method for enhancing line-to-line capacitance uniformity of plasma enhanced chemical vapor deposited (PECVD) inter-metal dielectric (IMD) layers' [patent_app_type] => B1 [patent_app_number] => 09/405057 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4990 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346476.pdf [firstpage_image] =>[orig_patent_app_number] => 09405057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405057
Method for enhancing line-to-line capacitance uniformity of plasma enhanced chemical vapor deposited (PECVD) inter-metal dielectric (IMD) layers Sep 26, 1999 Issued
Array ( [id] => 6674410 [patent_doc_number] => 20030060013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'METHOD OF MANUFACTURING TRENCH FIELD EFFECT TRANSISTORS WITH TRENCHED HEAVY BODY' [patent_app_type] => new [patent_app_number] => 09/405210 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2505 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20030060013.pdf [firstpage_image] =>[orig_patent_app_number] => 09405210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405210
METHOD OF MANUFACTURING TRENCH FIELD EFFECT TRANSISTORS WITH TRENCHED HEAVY BODY Sep 23, 1999 Abandoned
Array ( [id] => 4289734 [patent_doc_number] => 06235592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Type of high density vertical Mask ROM cell' [patent_app_type] => 1 [patent_app_number] => 9/400177 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2464 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235592.pdf [firstpage_image] =>[orig_patent_app_number] => 400177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400177
Type of high density vertical Mask ROM cell Sep 20, 1999 Issued
Array ( [id] => 1024483 [patent_doc_number] => 06884644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Low temperature formation of backside ohmic contacts for vertical devices' [patent_app_type] => utility [patent_app_number] => 09/787189 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4650 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884644.pdf [firstpage_image] =>[orig_patent_app_number] => 09787189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/787189
Low temperature formation of backside ohmic contacts for vertical devices Sep 15, 1999 Issued
Array ( [id] => 4358197 [patent_doc_number] => 06255168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for manufacturing bit line and bit line contact' [patent_app_type] => 1 [patent_app_number] => 9/394637 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1749 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255168.pdf [firstpage_image] =>[orig_patent_app_number] => 394637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394637
Method for manufacturing bit line and bit line contact Sep 12, 1999 Issued
Array ( [id] => 4408586 [patent_doc_number] => 06309968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method to improve intrinsic refresh time and dichlorosilane formed gate oxide reliability' [patent_app_type] => 1 [patent_app_number] => 9/391887 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2985 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309968.pdf [firstpage_image] =>[orig_patent_app_number] => 391887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391887
Method to improve intrinsic refresh time and dichlorosilane formed gate oxide reliability Sep 6, 1999 Issued
Array ( [id] => 4368632 [patent_doc_number] => 06287912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/389457 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9584 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287912.pdf [firstpage_image] =>[orig_patent_app_number] => 389457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389457
Method of fabricating semiconductor device Sep 2, 1999 Issued
Array ( [id] => 1453494 [patent_doc_number] => 06461915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method and structure for an improved floating gate memory cell' [patent_app_type] => B1 [patent_app_number] => 09/388287 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8201 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461915.pdf [firstpage_image] =>[orig_patent_app_number] => 09388287 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388287
Method and structure for an improved floating gate memory cell Aug 31, 1999 Issued
Array ( [id] => 1459491 [patent_doc_number] => 06391756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Semiconductor processing methods of forming contact openings' [patent_app_type] => B1 [patent_app_number] => 09/387040 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 2860 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391756.pdf [firstpage_image] =>[orig_patent_app_number] => 09387040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387040
Semiconductor processing methods of forming contact openings Aug 30, 1999 Issued
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