
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1566049
[patent_doc_number] => 06376370
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy'
[patent_app_type] => B1
[patent_app_number] => 09/484002
[patent_app_country] => US
[patent_app_date] => 2000-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
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[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/376/06376370.pdf
[firstpage_image] =>[orig_patent_app_number] => 09484002
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/484002 | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy | Jan 17, 2000 | Issued |
Array
(
[id] => 7636549
[patent_doc_number] => 06380108
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby'
[patent_app_type] => B1
[patent_app_number] => 09/468995
[patent_app_country] => US
[patent_app_date] => 1999-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4565
[patent_no_of_claims] => 85
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/380/06380108.pdf
[firstpage_image] =>[orig_patent_app_number] => 09468995
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/468995 | Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby | Dec 20, 1999 | Issued |
Array
(
[id] => 1092832
[patent_doc_number] => 06825087
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-30
[patent_title] => 'Hydrogen anneal for creating an enhanced trench for trench MOSFETS'
[patent_app_type] => B1
[patent_app_number] => 09/448884
[patent_app_country] => US
[patent_app_date] => 1999-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/825/06825087.pdf
[firstpage_image] =>[orig_patent_app_number] => 09448884
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/448884 | Hydrogen anneal for creating an enhanced trench for trench MOSFETS | Nov 23, 1999 | Issued |
Array
(
[id] => 4249496
[patent_doc_number] => 06207487
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Method for forming dielectric film of capacitor having different thicknesses partly'
[patent_app_type] => 1
[patent_app_number] => 9/415830
[patent_app_country] => US
[patent_app_date] => 1999-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 415830
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/415830 | Method for forming dielectric film of capacitor having different thicknesses partly | Oct 11, 1999 | Issued |
Array
(
[id] => 4368793
[patent_doc_number] => 06287923
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Method of forming a MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 9/414900
[patent_app_country] => US
[patent_app_date] => 1999-10-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/287/06287923.pdf
[firstpage_image] =>[orig_patent_app_number] => 414900
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/414900 | Method of forming a MOS transistor | Oct 7, 1999 | Issued |
Array
(
[id] => 4377236
[patent_doc_number] => 06303416
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Method to reduce plasma etch fluting'
[patent_app_type] => 1
[patent_app_number] => 9/414457
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[firstpage_image] =>[orig_patent_app_number] => 414457
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/414457 | Method to reduce plasma etch fluting | Oct 6, 1999 | Issued |
Array
(
[id] => 4286560
[patent_doc_number] => 06268243
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Method for fabricating dynamic random access memory cells'
[patent_app_type] => 1
[patent_app_number] => 9/413037
[patent_app_country] => US
[patent_app_date] => 1999-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
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[pdf_file] => patents/06/268/06268243.pdf
[firstpage_image] =>[orig_patent_app_number] => 413037
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/413037 | Method for fabricating dynamic random access memory cells | Oct 5, 1999 | Issued |
Array
(
[id] => 4408103
[patent_doc_number] => 06265257
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence'
[patent_app_type] => 1
[patent_app_number] => 9/409877
[patent_app_country] => US
[patent_app_date] => 1999-10-01
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3440
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[pdf_file] => patents/06/265/06265257.pdf
[firstpage_image] =>[orig_patent_app_number] => 409877
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/409877 | Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence | Sep 30, 1999 | Issued |
Array
(
[id] => 4395014
[patent_doc_number] => 06297122
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[patent_issue_date] => 2001-10-02
[patent_title] => 'Method of forming conductive film and capacitor'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 408837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/408837 | Method of forming conductive film and capacitor | Sep 29, 1999 | Issued |
Array
(
[id] => 5968490
[patent_doc_number] => 20020090769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-11
[patent_title] => 'LIQUID CRYSTAL DEVICE, LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => new
[patent_app_number] => 09/409266
[patent_app_country] => US
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[pdf_file] => publications/A1/0090/20020090769.pdf
[firstpage_image] =>[orig_patent_app_number] => 09409266
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/409266 | Liquid crystal device, liquid crystal display panel and method for manufacturing the same | Sep 29, 1999 | Issued |
Array
(
[id] => 4378792
[patent_doc_number] => 06303518
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers'
[patent_app_type] => 1
[patent_app_number] => 9/409580
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/409580 | Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers | Sep 29, 1999 | Issued |
Array
(
[id] => 1549836
[patent_doc_number] => 06346476
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[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Method for enhancing line-to-line capacitance uniformity of plasma enhanced chemical vapor deposited (PECVD) inter-metal dielectric (IMD) layers'
[patent_app_type] => B1
[patent_app_number] => 09/405057
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/405057 | Method for enhancing line-to-line capacitance uniformity of plasma enhanced chemical vapor deposited (PECVD) inter-metal dielectric (IMD) layers | Sep 26, 1999 | Issued |
Array
(
[id] => 6674410
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[patent_title] => 'METHOD OF MANUFACTURING TRENCH FIELD EFFECT TRANSISTORS WITH TRENCHED HEAVY BODY'
[patent_app_type] => new
[patent_app_number] => 09/405210
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/405210 | METHOD OF MANUFACTURING TRENCH FIELD EFFECT TRANSISTORS WITH TRENCHED HEAVY BODY | Sep 23, 1999 | Abandoned |
Array
(
[id] => 4289734
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[patent_issue_date] => 2001-05-22
[patent_title] => 'Type of high density vertical Mask ROM cell'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 400177
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/400177 | Type of high density vertical Mask ROM cell | Sep 20, 1999 | Issued |
Array
(
[id] => 1024483
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[patent_issue_date] => 2005-04-26
[patent_title] => 'Low temperature formation of backside ohmic contacts for vertical devices'
[patent_app_type] => utility
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Array
(
[id] => 4358197
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Method for manufacturing bit line and bit line contact'
[patent_app_type] => 1
[patent_app_number] => 9/394637
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/394637 | Method for manufacturing bit line and bit line contact | Sep 12, 1999 | Issued |
Array
(
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[patent_issue_date] => 2001-10-30
[patent_title] => 'Method to improve intrinsic refresh time and dichlorosilane formed gate oxide reliability'
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Array
(
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Array
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[patent_title] => 'Method and structure for an improved floating gate memory cell'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/388287 | Method and structure for an improved floating gate memory cell | Aug 31, 1999 | Issued |
Array
(
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[patent_title] => 'Semiconductor processing methods of forming contact openings'
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[firstpage_image] =>[orig_patent_app_number] => 09387040
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387040 | Semiconductor processing methods of forming contact openings | Aug 30, 1999 | Issued |