Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4303923 [patent_doc_number] => 06326277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Methods of forming recessed hemispherical grain silicon capacitor structures' [patent_app_type] => 1 [patent_app_number] => 9/385787 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5893 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326277.pdf [firstpage_image] =>[orig_patent_app_number] => 385787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385787
Methods of forming recessed hemispherical grain silicon capacitor structures Aug 29, 1999 Issued
Array ( [id] => 4357597 [patent_doc_number] => 06191001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Shallow trench isolation method' [patent_app_type] => 1 [patent_app_number] => 9/383050 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2694 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191001.pdf [firstpage_image] =>[orig_patent_app_number] => 383050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383050
Shallow trench isolation method Aug 24, 1999 Issued
Array ( [id] => 4369099 [patent_doc_number] => 06287944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Polycrystalline semiconductor device and its manufacture method' [patent_app_type] => 1 [patent_app_number] => 9/376827 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 5633 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287944.pdf [firstpage_image] =>[orig_patent_app_number] => 376827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376827
Polycrystalline semiconductor device and its manufacture method Aug 17, 1999 Issued
Array ( [id] => 4419940 [patent_doc_number] => 06177362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Fabrication method for gate structure having gate dielectric layers of different thickness' [patent_app_type] => 1 [patent_app_number] => 9/375877 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3626 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177362.pdf [firstpage_image] =>[orig_patent_app_number] => 375877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375877
Fabrication method for gate structure having gate dielectric layers of different thickness Aug 16, 1999 Issued
Array ( [id] => 4420721 [patent_doc_number] => 06225223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method to eliminate dishing of copper interconnects' [patent_app_type] => 1 [patent_app_number] => 9/374297 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1881 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225223.pdf [firstpage_image] =>[orig_patent_app_number] => 374297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374297
Method to eliminate dishing of copper interconnects Aug 15, 1999 Issued
Array ( [id] => 4350477 [patent_doc_number] => 06291308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Mask ROM fabrication method' [patent_app_type] => 1 [patent_app_number] => 9/372850 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 4901 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291308.pdf [firstpage_image] =>[orig_patent_app_number] => 372850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372850
Mask ROM fabrication method Aug 11, 1999 Issued
Array ( [id] => 1559671 [patent_doc_number] => 06436753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Semiconductor integrated circuit and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/372007 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 11126 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436753.pdf [firstpage_image] =>[orig_patent_app_number] => 09372007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372007
Semiconductor integrated circuit and method for manufacturing the same Aug 10, 1999 Issued
Array ( [id] => 4267210 [patent_doc_number] => 06306740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Manufacture of field emission element' [patent_app_type] => 1 [patent_app_number] => 9/371177 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 106 [patent_no_of_words] => 15556 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306740.pdf [firstpage_image] =>[orig_patent_app_number] => 371177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371177
Manufacture of field emission element Aug 9, 1999 Issued
Array ( [id] => 4318955 [patent_doc_number] => 06248654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for forming self-aligned contact' [patent_app_type] => 1 [patent_app_number] => 9/370880 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 3144 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248654.pdf [firstpage_image] =>[orig_patent_app_number] => 370880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370880
Method for forming self-aligned contact Aug 9, 1999 Issued
Array ( [id] => 1542631 [patent_doc_number] => 06372599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/371027 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 4716 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372599.pdf [firstpage_image] =>[orig_patent_app_number] => 09371027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371027
Semiconductor device and method of manufacturing the same Aug 9, 1999 Issued
Array ( [id] => 4358335 [patent_doc_number] => 06255178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for forming transistors with raised source and drains and device formed thereby' [patent_app_type] => 1 [patent_app_number] => 9/368767 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 40 [patent_no_of_words] => 11183 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255178.pdf [firstpage_image] =>[orig_patent_app_number] => 368767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368767
Method for forming transistors with raised source and drains and device formed thereby Aug 4, 1999 Issued
Array ( [id] => 1564884 [patent_doc_number] => 06338995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'High-permittivity dielectric capacitor for a semiconductor device and method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/368210 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1691 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338995.pdf [firstpage_image] =>[orig_patent_app_number] => 09368210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368210
High-permittivity dielectric capacitor for a semiconductor device and method for fabricating the same Aug 3, 1999 Issued
Array ( [id] => 1435928 [patent_doc_number] => 06355571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method and apparatus for reducing copper oxidation and contamination in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/365129 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3313 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355571.pdf [firstpage_image] =>[orig_patent_app_number] => 09365129 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365129
Method and apparatus for reducing copper oxidation and contamination in a semiconductor device Jul 29, 1999 Issued
Array ( [id] => 4329714 [patent_doc_number] => 06313044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Methods for forming a spin-on-glass layer' [patent_app_type] => 1 [patent_app_number] => 9/364330 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1808 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313044.pdf [firstpage_image] =>[orig_patent_app_number] => 364330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364330
Methods for forming a spin-on-glass layer Jul 29, 1999 Issued
Array ( [id] => 4395135 [patent_doc_number] => 06297131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Semiconductor device manufacturing method for grinding and dicing a wafer from a back side of the wafer' [patent_app_type] => 1 [patent_app_number] => 9/357657 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4335 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297131.pdf [firstpage_image] =>[orig_patent_app_number] => 357657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357657
Semiconductor device manufacturing method for grinding and dicing a wafer from a back side of the wafer Jul 19, 1999 Issued
Array ( [id] => 4249426 [patent_doc_number] => 06207482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Integration method for deep sub-micron dual gate transistor design' [patent_app_type] => 1 [patent_app_number] => 9/346528 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4731 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207482.pdf [firstpage_image] =>[orig_patent_app_number] => 346528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346528
Integration method for deep sub-micron dual gate transistor design Jul 1, 1999 Issued
Array ( [id] => 4155447 [patent_doc_number] => 06156587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method of attaching solid state imaging device' [patent_app_type] => 1 [patent_app_number] => 9/259292 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3126 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156587.pdf [firstpage_image] =>[orig_patent_app_number] => 259292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259292
Method of attaching solid state imaging device Feb 28, 1999 Issued
Array ( [id] => 4405746 [patent_doc_number] => 06232212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Flip chip bump bonding' [patent_app_type] => 1 [patent_app_number] => 9/256443 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3432 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232212.pdf [firstpage_image] =>[orig_patent_app_number] => 256443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256443
Flip chip bump bonding Feb 22, 1999 Issued
Array ( [id] => 4302232 [patent_doc_number] => 06187612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Molded ball grid array package mold die' [patent_app_type] => 1 [patent_app_number] => 9/250642 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187612.pdf [firstpage_image] =>[orig_patent_app_number] => 250642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250642
Molded ball grid array package mold die Feb 15, 1999 Issued
Array ( [id] => 4347371 [patent_doc_number] => 06214645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method of molding ball grid array semiconductor packages' [patent_app_type] => 1 [patent_app_number] => 9/240423 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6780 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214645.pdf [firstpage_image] =>[orig_patent_app_number] => 240423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/240423
Method of molding ball grid array semiconductor packages Jan 28, 1999 Issued
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