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David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4405185 [patent_doc_number] => 06232162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method of complementary metal-oxide semiconductor' [patent_app_type] => 1 [patent_app_number] => 9/236932 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2280 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232162.pdf [firstpage_image] =>[orig_patent_app_number] => 236932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236932
Method of complementary metal-oxide semiconductor Jan 24, 1999 Issued
Array ( [id] => 4356736 [patent_doc_number] => 06190940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Flip chip assembly of semiconductor IC chips' [patent_app_type] => 1 [patent_app_number] => 9/235011 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4492 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190940.pdf [firstpage_image] =>[orig_patent_app_number] => 235011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/235011
Flip chip assembly of semiconductor IC chips Jan 20, 1999 Issued
Array ( [id] => 6141708 [patent_doc_number] => 20020001872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR ELEMENT MOUNTING STRUCTURE OF SEMICONDUCTOR PACKAGE MOUNTED ON CIRCUIT BOARD AND METHOD OF ASSEMBLING SEMICONDUCTOR PACKAGE' [patent_app_type] => new [patent_app_number] => 09/231663 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5424 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001872.pdf [firstpage_image] =>[orig_patent_app_number] => 09231663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231663
Semiconductor package having semiconductor element mounting structure of semiconductor package mounted on circuit board and method of assembling semiconductor package Jan 14, 1999 Issued
Array ( [id] => 4356936 [patent_doc_number] => 06190954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Robust latchup-immune CMOS structure' [patent_app_type] => 1 [patent_app_number] => 9/229381 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2482 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190954.pdf [firstpage_image] =>[orig_patent_app_number] => 229381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229381
Robust latchup-immune CMOS structure Jan 10, 1999 Issued
Array ( [id] => 4182020 [patent_doc_number] => 06150205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method of fabricating dual gate' [patent_app_type] => 1 [patent_app_number] => 9/227761 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1864 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150205.pdf [firstpage_image] =>[orig_patent_app_number] => 227761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227761
Method of fabricating dual gate Jan 7, 1999 Issued
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