Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15905965 [patent_doc_number] => 20200152503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => INTEGRATED ELECTRONIC CIRCUIT WITH AIRGAPS [patent_app_type] => utility [patent_app_number] => 16/577332 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577332
Integrated electronic circuit with airgaps Sep 19, 2019 Issued
Array ( [id] => 15351561 [patent_doc_number] => 20200013672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => CAP STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/573209 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573209
Cap structure Sep 16, 2019 Issued
Array ( [id] => 15331655 [patent_doc_number] => 20200006157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Method for Patterning a Lanthanum Containing Layer [patent_app_type] => utility [patent_app_number] => 16/569820 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569820
Method for patterning a lanthanum containing layer Sep 12, 2019 Issued
Array ( [id] => 18857511 [patent_doc_number] => 11855108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Solid-state imaging element and electronic device [patent_app_type] => utility [patent_app_number] => 17/250708 [patent_app_country] => US [patent_app_date] => 2019-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5658 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250708
Solid-state imaging element and electronic device Sep 1, 2019 Issued
Array ( [id] => 16699926 [patent_doc_number] => 10950534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Through-substrate via structure and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/545139 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545139
Through-substrate via structure and method of manufacture Aug 19, 2019 Issued
Array ( [id] => 16448457 [patent_doc_number] => 10840388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Varactor with hyper-abrupt junction region including a superlattice [patent_app_type] => utility [patent_app_number] => 16/513932 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5770 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513932
Varactor with hyper-abrupt junction region including a superlattice Jul 16, 2019 Issued
Array ( [id] => 16586432 [patent_doc_number] => 20210020834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/513745 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513745
Memory device and a method for forming the memory device Jul 16, 2019 Issued
Array ( [id] => 16210615 [patent_doc_number] => 20200243605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A DATA STORAGE PATTERN AND A METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/513925 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513925
Semiconductor device including a data storage pattern and a method of manufacturing the same Jul 16, 2019 Issued
Array ( [id] => 17590827 [patent_doc_number] => 11329104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 16/496630 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3306 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16496630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/496630
Display panel and display device Jul 11, 2019 Issued
Array ( [id] => 18175193 [patent_doc_number] => 11574910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Device with air-gaps to reduce coupling capacitance and process for forming such [patent_app_type] => utility [patent_app_number] => 16/457677 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6943 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457677
Device with air-gaps to reduce coupling capacitance and process for forming such Jun 27, 2019 Issued
Array ( [id] => 14938631 [patent_doc_number] => 20190304954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => 3D IC PACKAGE WITH RDL INTERPOSER AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 16/447335 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447335
3D IC package with RDL interposer and related method Jun 19, 2019 Issued
Array ( [id] => 14938811 [patent_doc_number] => 20190305044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/447370 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447370
Memory device and method of manufacturing the same Jun 19, 2019 Issued
Array ( [id] => 16865811 [patent_doc_number] => 11024564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Packaged electronic device with film isolated power stack [patent_app_type] => utility [patent_app_number] => 16/445836 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445836 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445836
Packaged electronic device with film isolated power stack Jun 18, 2019 Issued
Array ( [id] => 15351921 [patent_doc_number] => 20200013852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => METAL-INSULATOR METAL STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/445290 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445290
Metal-insulator metal structure and method of forming the same Jun 18, 2019 Issued
Array ( [id] => 16042691 [patent_doc_number] => 10683204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor arrangement and formation thereof [patent_app_type] => utility [patent_app_number] => 16/443174 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443174
Semiconductor arrangement and formation thereof Jun 16, 2019 Issued
Array ( [id] => 20205661 [patent_doc_number] => 12408458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Photoelectric conversion element and light receiving device [patent_app_type] => utility [patent_app_number] => 17/250329 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 51 [patent_no_of_words] => 22947 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250329
Photoelectric conversion element and light receiving device Jun 13, 2019 Issued
Array ( [id] => 18236175 [patent_doc_number] => 11600743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => High efficient microdevices [patent_app_type] => utility [patent_app_number] => 16/428103 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 97 [patent_no_of_words] => 22182 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/428103
High efficient microdevices May 30, 2019 Issued
Array ( [id] => 15756725 [patent_doc_number] => 10620471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Curved display [patent_app_type] => utility [patent_app_number] => 16/421070 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8212 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/421070
Curved display May 22, 2019 Issued
Array ( [id] => 15922091 [patent_doc_number] => 10658294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Structure and method for flexible power staple insertion [patent_app_type] => utility [patent_app_number] => 16/411237 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411237
Structure and method for flexible power staple insertion May 13, 2019 Issued
Array ( [id] => 14784791 [patent_doc_number] => 20190267293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Strain Enhancement for FinFETs [patent_app_type] => utility [patent_app_number] => 16/410127 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410127 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410127
Strain enhancement for FinFETs May 12, 2019 Issued
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