
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12250089
[patent_doc_number] => 09922871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-20
[patent_title] => 'Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 15/401896
[patent_app_country] => US
[patent_app_date] => 2017-01-09
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401896
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/401896 | Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit | Jan 8, 2017 | Issued |
Array
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[id] => 11732894
[patent_doc_number] => 20170194337
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'NEUROMORPHIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/394548
[patent_app_country] => US
[patent_app_date] => 2016-12-29
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Array
(
[id] => 11571801
[patent_doc_number] => 20170110445
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'SEMICONDUCTOR DEVICES HAVING HYBRID STACKING STRUCTURES AND METHODS OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/391424
[patent_app_country] => US
[patent_app_date] => 2016-12-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/391424 | SEMICONDUCTOR DEVICES HAVING HYBRID STACKING STRUCTURES AND METHODS OF FABRICATING THE SAME | Dec 26, 2016 | Abandoned |
Array
(
[id] => 11760361
[patent_doc_number] => 20170207230
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-20
[patent_title] => 'SINGLE-POLY NONVOLATILE MEMORY CELL STRUCTURE HAVING AN ERASE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/384323
[patent_app_country] => US
[patent_app_date] => 2016-12-20
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384323 | Single-poly nonvolatile memory cell structure having an erase device | Dec 19, 2016 | Issued |
Array
(
[id] => 13667317
[patent_doc_number] => 10163837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Cu pillar bump with L-shaped non-metal sidewall protection structure
[patent_app_type] => utility
[patent_app_number] => 15/368936
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/368936 | Cu pillar bump with L-shaped non-metal sidewall protection structure | Dec 4, 2016 | Issued |
Array
(
[id] => 12954175
[patent_doc_number] => 09837539
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[patent_issue_date] => 2017-12-05
[patent_title] => FinFET device and method of forming
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[patent_app_number] => 15/363273
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363273 | FinFET device and method of forming | Nov 28, 2016 | Issued |
Array
(
[id] => 12945196
[patent_doc_number] => 09834435
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[patent_title] => Structure and formation method of semiconductor device structure
[patent_app_type] => utility
[patent_app_number] => 15/363389
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363389 | Structure and formation method of semiconductor device structure | Nov 28, 2016 | Issued |
Array
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[id] => 11681229
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[patent_issue_date] => 2017-06-13
[patent_title] => 'Semiconductor device structures comprising polycrystalline CVD diamond with improved near-substrate thermal conductivity'
[patent_app_type] => utility
[patent_app_number] => 15/356881
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/356881 | Semiconductor device structures comprising polycrystalline CVD diamond with improved near-substrate thermal conductivity | Nov 20, 2016 | Issued |
Array
(
[id] => 11475880
[patent_doc_number] => 20170062664
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[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'LIGHT EMITTING DIODE PACKAGE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 15/351380
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/351380 | LIGHT EMITTING DIODE PACKAGE STRUCTURE | Nov 13, 2016 | Abandoned |
Array
(
[id] => 13019443
[patent_doc_number] => 10032841
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[patent_kind] => B2
[patent_issue_date] => 2018-07-24
[patent_title] => Silicon and semiconducting oxide thin-film transistor displays
[patent_app_type] => utility
[patent_app_number] => 15/351266
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/351266 | Silicon and semiconducting oxide thin-film transistor displays | Nov 13, 2016 | Issued |
Array
(
[id] => 11876458
[patent_doc_number] => 09748239
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[patent_issue_date] => 2017-08-29
[patent_title] => 'Fin-double-gated junction field effect transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/347326 | Fin-double-gated junction field effect transistor | Nov 8, 2016 | Issued |
Array
(
[id] => 11623150
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[patent_title] => 'INTERCONNECT STRUCTURES AND METHODS FOR FABRICATING INTERCONNECT STRUCTURES'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/342444 | Interconnect structures and methods for fabricating interconnect structures | Nov 2, 2016 | Issued |
Array
(
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[patent_title] => 'MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME'
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Array
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[patent_title] => 'Resistor and capacitor disposed directly upon a SAC cap of a gate structure of a semiconductor structure'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/290849 | Packages for integrated circuits and methods of packaging integrated circuits | Oct 10, 2016 | Issued |