Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11740222 [patent_doc_number] => 09704815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Package substrate and semiconductor package including the same' [patent_app_type] => utility [patent_app_number] => 15/156327 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4320 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15156327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/156327
Package substrate and semiconductor package including the same May 15, 2016 Issued
Array ( [id] => 12054472 [patent_doc_number] => 20170330815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'MOUNTING AND ENVIRONMENTAL PROTECTION DEVICE FOR AN IGBT MODULE' [patent_app_type] => utility [patent_app_number] => 15/156169 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15156169 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/156169
Mounting and environmental protection device for an IGBT module May 15, 2016 Issued
Array ( [id] => 11293946 [patent_doc_number] => 20160343878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'Thin Film Transistor Substrate Having High Reliability Metal Oxide Semiconductor Material' [patent_app_type] => utility [patent_app_number] => 15/156263 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6903 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15156263 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/156263
Thin film transistor substrate having high reliability metal oxide semiconductor material May 15, 2016 Issued
Array ( [id] => 16218616 [patent_doc_number] => 10734439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Method for producing an optoelectronic device comprising a plurality of gallium nitride diodes [patent_app_type] => utility [patent_app_number] => 16/095335 [patent_app_country] => US [patent_app_date] => 2016-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4797 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16095335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/095335
Method for producing an optoelectronic device comprising a plurality of gallium nitride diodes May 12, 2016 Issued
Array ( [id] => 11740266 [patent_doc_number] => 09704859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-11 [patent_title] => 'Forming semiconductor fins with self-aligned patterning' [patent_app_type] => utility [patent_app_number] => 15/148052 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 54 [patent_no_of_words] => 7042 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148052 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148052
Forming semiconductor fins with self-aligned patterning May 5, 2016 Issued
Array ( [id] => 11050919 [patent_doc_number] => 20160247878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'Isolation Trench Fill Using Oxide Liner and Nitride Etch Back Technique With Dual Trench Depth Capability' [patent_app_type] => utility [patent_app_number] => 15/147242 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2165 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147242
Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability May 4, 2016 Issued
Array ( [id] => 11510322 [patent_doc_number] => 09601488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Gate-all-around semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 15/138056 [patent_app_country] => US [patent_app_date] => 2016-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 7690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15138056 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/138056
Gate-all-around semiconductor device and method of fabricating the same Apr 24, 2016 Issued
Array ( [id] => 11028712 [patent_doc_number] => 20160225668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'TSV Formation Processes Using TSV-Last Approach' [patent_app_type] => utility [patent_app_number] => 15/094207 [patent_app_country] => US [patent_app_date] => 2016-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15094207 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/094207
TSV formation processes using TSV-last approach Apr 7, 2016 Issued
Array ( [id] => 10996678 [patent_doc_number] => 20160193623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'DEPOSITION MASK, PRODUCING METHOD THEREFOR AND FORMING METHOD FOR THIN FILM PATTERN' [patent_app_type] => utility [patent_app_number] => 15/071116 [patent_app_country] => US [patent_app_date] => 2016-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 26300 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15071116 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/071116
Deposition mask, producing method therefor and forming method for thin film pattern Mar 14, 2016 Issued
Array ( [id] => 10997798 [patent_doc_number] => 20160194745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'DEPOSITION MASK, PRODUCING METHOD THEREFOR AND FORMING METHOD FOR THIN FILM PATTERN' [patent_app_type] => utility [patent_app_number] => 15/071125 [patent_app_country] => US [patent_app_date] => 2016-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 26302 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15071125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/071125
Deposition mask, producing method therefor and forming method for thin film pattern Mar 14, 2016 Issued
Array ( [id] => 11000206 [patent_doc_number] => 20160197153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED FLOATING GATES' [patent_app_type] => utility [patent_app_number] => 15/069282 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9966 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15069282 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/069282
Nonvolatile memory devices having single-layered floating gates Mar 13, 2016 Issued
Array ( [id] => 14024447 [patent_doc_number] => 20190074217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => CONDUCTIVE CONNECTORS HAVING A RUTHENIUM/ALUMINUM-CONTAINING LINER AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/072145 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16072145 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/072145
CONDUCTIVE CONNECTORS HAVING A RUTHENIUM/ALUMINUM-CONTAINING LINER AND METHODS OF FABRICATING THE SAME Feb 24, 2016 Abandoned
Array ( [id] => 11578591 [patent_doc_number] => 09633859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Semiconductor device and a manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/043579 [patent_app_country] => US [patent_app_date] => 2016-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 44 [patent_no_of_words] => 30129 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/043579
Semiconductor device and a manufacturing method thereof Feb 13, 2016 Issued
Array ( [id] => 11876625 [patent_doc_number] => 09748407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Semiconductor device and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 15/043569 [patent_app_country] => US [patent_app_date] => 2016-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 17516 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 475 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/043569
Semiconductor device and method of manufacturing same Feb 13, 2016 Issued
Array ( [id] => 11891047 [patent_doc_number] => 09761611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/016451 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 41 [patent_no_of_words] => 23203 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016451
Semiconductor device Feb 4, 2016 Issued
Array ( [id] => 11360133 [patent_doc_number] => 09536789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-03 [patent_title] => 'Fin-double-gated junction field effect transistor' [patent_app_type] => utility [patent_app_number] => 15/007616 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6991 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007616 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/007616
Fin-double-gated junction field effect transistor Jan 26, 2016 Issued
Array ( [id] => 11007322 [patent_doc_number] => 20160204274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'NON-VOLATILE MEMORY UNIT AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/994852 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8153 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994852 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994852
Non-volatile memory unit and method for manufacturing the same Jan 12, 2016 Issued
Array ( [id] => 11475613 [patent_doc_number] => 20170062396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'TILED HYBRID ARRAY AND METHOD OF FORMING' [patent_app_type] => utility [patent_app_number] => 14/994917 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2322 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994917 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994917
Tiled hybrid array and method of forming Jan 12, 2016 Issued
Array ( [id] => 11300741 [patent_doc_number] => 09508753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Display apparatus' [patent_app_type] => utility [patent_app_number] => 14/992339 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3870 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992339 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/992339
Display apparatus Jan 10, 2016 Issued
Array ( [id] => 11391819 [patent_doc_number] => 09553071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-24 [patent_title] => 'Multi-chip package with interconnects extending through logic chip' [patent_app_type] => utility [patent_app_number] => 14/992178 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/992178
Multi-chip package with interconnects extending through logic chip Jan 10, 2016 Issued
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