
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_title] => 'Thin Film Transistor Substrate Having High Reliability Metal Oxide Semiconductor Material'
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[patent_title] => Method for producing an optoelectronic device comprising a plurality of gallium nitride diodes
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Array
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