
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11225212
[patent_doc_number] => 09452926
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-09-27
[patent_title] => 'Dopant selective reactive ion etching of silicon carbide'
[patent_app_type] => utility
[patent_app_number] => 13/561359
[patent_app_country] => US
[patent_app_date] => 2012-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561359
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/561359 | Dopant selective reactive ion etching of silicon carbide | Jul 29, 2012 | Issued |
Array
(
[id] => 9817522
[patent_doc_number] => 08927305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-06
[patent_title] => 'Method of manufacturing light emitting device'
[patent_app_type] => utility
[patent_app_number] => 13/562019
[patent_app_country] => US
[patent_app_date] => 2012-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562019
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/562019 | Method of manufacturing light emitting device | Jul 29, 2012 | Issued |
Array
(
[id] => 9280868
[patent_doc_number] => 20140030836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'Silicon Carbide Lamina'
[patent_app_type] => utility
[patent_app_number] => 13/558843
[patent_app_country] => US
[patent_app_date] => 2012-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558843
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/558843 | Silicon carbide lamina | Jul 25, 2012 | Issued |
Array
(
[id] => 9280892
[patent_doc_number] => 20140030860
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'MANUFACTURING METHOD OF TUNNEL OXIDE OF NOR FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/556490
[patent_app_country] => US
[patent_app_date] => 2012-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1394
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13556490
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/556490 | MANUFACTURING METHOD OF TUNNEL OXIDE OF NOR FLASH MEMORY | Jul 23, 2012 | Abandoned |
Array
(
[id] => 9817581
[patent_doc_number] => 08927365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-06
[patent_title] => 'Method of eDRAM DT strap formation in FinFET device structure'
[patent_app_type] => utility
[patent_app_number] => 13/556437
[patent_app_country] => US
[patent_app_date] => 2012-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13556437
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/556437 | Method of eDRAM DT strap formation in FinFET device structure | Jul 23, 2012 | Issued |
Array
(
[id] => 10844358
[patent_doc_number] => 08871533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Method for making solar cell and solar cell system'
[patent_app_type] => utility
[patent_app_number] => 13/556279
[patent_app_country] => US
[patent_app_date] => 2012-07-24
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/556279 | Method for making solar cell and solar cell system | Jul 23, 2012 | Issued |
Array
(
[id] => 8617772
[patent_doc_number] => 20130023084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-24
[patent_title] => 'Substrate for Use in Preparing Solar Cells'
[patent_app_type] => utility
[patent_app_number] => 13/554227
[patent_app_country] => US
[patent_app_date] => 2012-07-20
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13554227
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/554227 | Substrate for use in preparing solar cells | Jul 19, 2012 | Issued |
Array
(
[id] => 9269270
[patent_doc_number] => 20140024186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-23
[patent_title] => 'METHOD FOR FORMING DUAL GATE INSULATION LAYERS AND SEMICONDUCTOR DEVICE HAVING DUAL GATE INSULATION LAYERS'
[patent_app_type] => utility
[patent_app_number] => 13/554665
[patent_app_country] => US
[patent_app_date] => 2012-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 10300
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13554665
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/554665 | Method for forming dual gate insulation layers and semiconductor device having dual gate insulation layers | Jul 19, 2012 | Issued |
Array
(
[id] => 9710627
[patent_doc_number] => 08835195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-16
[patent_title] => 'Corrugated membrane MEMS actuator fabrication method'
[patent_app_type] => utility
[patent_app_number] => 13/552721
[patent_app_country] => US
[patent_app_date] => 2012-07-19
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/552721 | Corrugated membrane MEMS actuator fabrication method | Jul 18, 2012 | Issued |
Array
(
[id] => 8659601
[patent_doc_number] => 20130040430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-14
[patent_title] => 'FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A NITRIDE BASED HARD MASK LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/552722
[patent_app_country] => US
[patent_app_date] => 2012-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13552722
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/552722 | Formation of a channel semiconductor alloy by forming a nitride based hard mask layer | Jul 18, 2012 | Issued |
Array
(
[id] => 9059785
[patent_doc_number] => 08546220
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-10-01
[patent_title] => 'Method for fabricating buried bit lines'
[patent_app_type] => utility
[patent_app_number] => 13/551919
[patent_app_country] => US
[patent_app_date] => 2012-07-18
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551919
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/551919 | Method for fabricating buried bit lines | Jul 17, 2012 | Issued |
Array
(
[id] => 9269268
[patent_doc_number] => 20140024185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-23
[patent_title] => 'SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 13/551776
[patent_app_country] => US
[patent_app_date] => 2012-07-18
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551776
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/551776 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Jul 17, 2012 | Issued |
Array
(
[id] => 8960825
[patent_doc_number] => 20130200427
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[patent_issue_date] => 2013-08-08
[patent_title] => 'TRANSISTORS AND METHODS OF MANUFACTURING THE SAME'
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[patent_app_number] => 13/550032
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/550032 | Transistors and methods of manufacturing the same | Jul 15, 2012 | Issued |
Array
(
[id] => 9440765
[patent_doc_number] => 08709875
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-29
[patent_title] => 'Power device and method of packaging same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/549518 | Power device and method of packaging same | Jul 15, 2012 | Issued |
Array
(
[id] => 8647147
[patent_doc_number] => 20130032877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-07
[patent_title] => 'N-CHANNEL TRANSISTOR COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE AND A REDUCED SERIES RESISTANCE BY EPITAXIALLY FORMED SEMICONDUCTOR MATERIAL IN THE DRAIN AND SOURCE AREAS'
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Array
(
[id] => 8610114
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[patent_app_type] => utility
[patent_app_number] => 13/549391
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/549391 | Method of manufacturing of a semi-conductor element and semi-conductor element | Jul 12, 2012 | Issued |
Array
(
[id] => 10870151
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[patent_issue_date] => 2014-11-25
[patent_title] => 'Solid-state imaging device, manufacturing method for the same, and imaging apparatus'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/539229 | Wafer-level packaging mechanisms | Jun 28, 2012 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/530381 | Redeposition control in MRAM fabrication process | Jun 21, 2012 | Issued |