Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9662949 [patent_doc_number] => 08809933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Bit line structure, semiconductor device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 12/834212 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4221 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12834212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834212
Bit line structure, semiconductor device and method of forming the same Jul 11, 2010 Issued
Array ( [id] => 8759948 [patent_doc_number] => 08420469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Schottky FET fabricated with gate last process' [patent_app_type] => utility [patent_app_number] => 12/834428 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2195 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12834428 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834428
Schottky FET fabricated with gate last process Jul 11, 2010 Issued
Array ( [id] => 8533807 [patent_doc_number] => 08309964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor' [patent_app_type] => utility [patent_app_number] => 12/834195 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3828 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12834195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834195
Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor Jul 11, 2010 Issued
Array ( [id] => 6184174 [patent_doc_number] => 20110169159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'CHIP PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/816301 [patent_app_country] => US [patent_app_date] => 2010-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20110169159.pdf [firstpage_image] =>[orig_patent_app_number] => 12816301 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/816301
Chip package and fabrication method thereof Jun 14, 2010 Issued
Array ( [id] => 6273910 [patent_doc_number] => 20100255678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'Method of depositing a uniform metal seed layer over a plurality of recessed semiconductor features' [patent_app_type] => utility [patent_app_number] => 12/802701 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7998 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20100255678.pdf [firstpage_image] =>[orig_patent_app_number] => 12802701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/802701
Method of depositing a uniform metal seed layer over a plurality of recessed semiconductor features Jun 10, 2010 Issued
Array ( [id] => 8329056 [patent_doc_number] => 08237148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => '4F2 self align side wall active phase change memory' [patent_app_type] => utility [patent_app_number] => 12/792604 [patent_app_country] => US [patent_app_date] => 2010-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 9177 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12792604 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/792604
4F2 self align side wall active phase change memory Jun 1, 2010 Issued
Array ( [id] => 6540251 [patent_doc_number] => 20100221865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Crosstalk Improvement Through P On N Structure For Image Sensor' [patent_app_type] => utility [patent_app_number] => 12/780625 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3678 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20100221865.pdf [firstpage_image] =>[orig_patent_app_number] => 12780625 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/780625
Crosstalk improvement through P on N structure for image sensor May 13, 2010 Issued
Array ( [id] => 6540772 [patent_doc_number] => 20100221904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Process for Manufacturing a Non-Volatile Memory Electronic Device Integrated on a Semiconductor Substrate and Corresponding Device' [patent_app_type] => utility [patent_app_number] => 12/779150 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5719 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20100221904.pdf [firstpage_image] =>[orig_patent_app_number] => 12779150 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/779150
Process for Manufacturing a Non-Volatile Memory Electronic Device Integrated on a Semiconductor Substrate and Corresponding Device May 12, 2010 Abandoned
Array ( [id] => 6540840 [patent_doc_number] => 20100221910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'METHOD OF PRODUCING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/778288 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9047 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20100221910.pdf [firstpage_image] =>[orig_patent_app_number] => 12778288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/778288
METHOD OF PRODUCING SEMICONDUCTOR DEVICE May 11, 2010 Abandoned
Array ( [id] => 4634420 [patent_doc_number] => 08012871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/771494 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8331 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/012/08012871.pdf [firstpage_image] =>[orig_patent_app_number] => 12771494 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/771494
Semiconductor device and manufacturing method thereof Apr 29, 2010 Issued
Array ( [id] => 7496792 [patent_doc_number] => 20110260232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'DEVICE INCLUDING MEMORY ARRAY AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/765731 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260232.pdf [firstpage_image] =>[orig_patent_app_number] => 12765731 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765731
Device including memory array and method thereof Apr 21, 2010 Issued
Array ( [id] => 6528746 [patent_doc_number] => 20100203698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/763324 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20100203698.pdf [firstpage_image] =>[orig_patent_app_number] => 12763324 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763324
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE Apr 19, 2010 Abandoned
Array ( [id] => 6507868 [patent_doc_number] => 20100219501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'TRENCH ISOLATION IMPLANTATION' [patent_app_type] => utility [patent_app_number] => 12/758488 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219501.pdf [firstpage_image] =>[orig_patent_app_number] => 12758488 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758488
Trench isolation implantation Apr 11, 2010 Issued
Array ( [id] => 6310927 [patent_doc_number] => 20100193797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Stacked transistors and electronic devices including the same' [patent_app_type] => utility [patent_app_number] => 12/662272 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2434 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20100193797.pdf [firstpage_image] =>[orig_patent_app_number] => 12662272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662272
Stacked transistors and electronic devices including the same Apr 7, 2010 Issued
Array ( [id] => 8871178 [patent_doc_number] => 08466557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Solder bump confinement system for an integrated circuit package' [patent_app_type] => utility [patent_app_number] => 12/756067 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4194 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12756067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756067
Solder bump confinement system for an integrated circuit package Apr 6, 2010 Issued
Array ( [id] => 6461149 [patent_doc_number] => 20100190306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM' [patent_app_type] => utility [patent_app_number] => 12/754097 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 11080 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20100190306.pdf [firstpage_image] =>[orig_patent_app_number] => 12754097 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754097
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM Apr 4, 2010 Abandoned
Array ( [id] => 6324137 [patent_doc_number] => 20100197074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 12/753615 [patent_app_country] => US [patent_app_date] => 2010-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4973 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20100197074.pdf [firstpage_image] =>[orig_patent_app_number] => 12753615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/753615
Thin film transistor array panel and method of manufacture Apr 1, 2010 Issued
Array ( [id] => 6398678 [patent_doc_number] => 20100178739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'INTEGRATION SCHEME FOR AN NMOS METAL GATE' [patent_app_type] => utility [patent_app_number] => 12/731900 [patent_app_country] => US [patent_app_date] => 2010-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6557 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20100178739.pdf [firstpage_image] =>[orig_patent_app_number] => 12731900 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731900
Integration scheme for an NMOS metal gate Mar 24, 2010 Issued
Array ( [id] => 6280266 [patent_doc_number] => 20100155822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE OF SMALL RESISTANCE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/717753 [patent_app_country] => US [patent_app_date] => 2010-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7463 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155822.pdf [firstpage_image] =>[orig_patent_app_number] => 12717753 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717753
Semiconductor memory device with bit line of small resistance and manufacturing method thereof Mar 3, 2010 Issued
Array ( [id] => 6400671 [patent_doc_number] => 20100148300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'ISOLATION TRENCH FILL USING OXIDE LINER AND NITRIDE ETCH BACK TECHNIQUE WITH DUAL TRENCH DEPTH CAPABILITY' [patent_app_type] => utility [patent_app_number] => 12/712401 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2165 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148300.pdf [firstpage_image] =>[orig_patent_app_number] => 12712401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712401
Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability Feb 24, 2010 Issued
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