
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5278711
[patent_doc_number] => 20090130843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-21
[patent_title] => 'METHOD OF FORMING LOW-RESISTIVITY RECESSED FEATURES IN COPPER METALLIZATION'
[patent_app_type] => utility
[patent_app_number] => 11/864960
[patent_app_country] => US
[patent_app_date] => 2007-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6677
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20090130843.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864960
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864960 | Method of forming low-resistivity recessed features in copper metallization | Nov 19, 2007 | Issued |
Array
(
[id] => 4719517
[patent_doc_number] => 20080242040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 11/942400
[patent_app_country] => US
[patent_app_date] => 2007-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8113
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20080242040.pdf
[firstpage_image] =>[orig_patent_app_number] => 11942400
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/942400 | Method of forming a semiconductor structure | Nov 18, 2007 | Issued |
Array
(
[id] => 4829320
[patent_doc_number] => 20080128825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/979870
[patent_app_country] => US
[patent_app_date] => 2007-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 15741
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20080128825.pdf
[firstpage_image] =>[orig_patent_app_number] => 11979870
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/979870 | Semiconductor device and method for fabricating the same | Nov 8, 2007 | Abandoned |
Array
(
[id] => 8165610
[patent_doc_number] => 08174012
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-08
[patent_title] => 'Organic light emitting diode display device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/935670
[patent_app_country] => US
[patent_app_date] => 2007-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 7022
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/174/08174012.pdf
[firstpage_image] =>[orig_patent_app_number] => 11935670
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/935670 | Organic light emitting diode display device and method of manufacturing the same | Nov 5, 2007 | Issued |
Array
(
[id] => 9216221
[patent_doc_number] => 08629021
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-14
[patent_title] => 'Integration scheme for an NMOS metal gate'
[patent_app_type] => utility
[patent_app_number] => 11/934250
[patent_app_country] => US
[patent_app_date] => 2007-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 26
[patent_no_of_words] => 6526
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11934250
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934250 | Integration scheme for an NMOS metal gate | Nov 1, 2007 | Issued |
Array
(
[id] => 4723957
[patent_doc_number] => 20080203498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/933845
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6620
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0203/20080203498.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933845
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933845 | Semiconductor device and manufacturing method of semiconductor device | Oct 31, 2007 | Issued |
Array
(
[id] => 5262264
[patent_doc_number] => 20090114949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'HIGH-MOBILITY TRENCH MOSFETS'
[patent_app_type] => utility
[patent_app_number] => 11/934040
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 5458
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20090114949.pdf
[firstpage_image] =>[orig_patent_app_number] => 11934040
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934040 | High-mobility trench MOSFETs | Oct 31, 2007 | Issued |
Array
(
[id] => 4495618
[patent_doc_number] => 07947553
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-24
[patent_title] => 'Method for fabricating semiconductor device with recess gate'
[patent_app_type] => utility
[patent_app_number] => 11/931510
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 3358
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/947/07947553.pdf
[firstpage_image] =>[orig_patent_app_number] => 11931510
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/931510 | Method for fabricating semiconductor device with recess gate | Oct 30, 2007 | Issued |
Array
(
[id] => 151722
[patent_doc_number] => 07678689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-16
[patent_title] => 'Method of fabricating memory device'
[patent_app_type] => utility
[patent_app_number] => 11/931400
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2943
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/678/07678689.pdf
[firstpage_image] =>[orig_patent_app_number] => 11931400
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/931400 | Method of fabricating memory device | Oct 30, 2007 | Issued |
Array
(
[id] => 5327862
[patent_doc_number] => 20090108339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-30
[patent_title] => 'HIGH VOLTAGE TMOS SEMICONDUCTOR DEVICE WITH LOW GATE CHARGE STRUCTURE AND METHOD OF MAKING'
[patent_app_type] => utility
[patent_app_number] => 11/932070
[patent_app_country] => US
[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5629
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20090108339.pdf
[firstpage_image] =>[orig_patent_app_number] => 11932070
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/932070 | High voltage TMOS semiconductor device with low gate charge structure and method of making | Oct 30, 2007 | Issued |
Array
(
[id] => 4749106
[patent_doc_number] => 20080157177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Flash Device and the Manufacturing Method'
[patent_app_type] => utility
[patent_app_number] => 11/929900
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2254
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20080157177.pdf
[firstpage_image] =>[orig_patent_app_number] => 11929900
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/929900 | Flash device and the manufacturing method | Oct 29, 2007 | Issued |
Array
(
[id] => 6423130
[patent_doc_number] => 20100102446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'SEMICONDUCTOR ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/447658
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 18316
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20100102446.pdf
[firstpage_image] =>[orig_patent_app_number] => 12447658
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/447658 | Semiconductor electronic component and semiconductor device using the same | Oct 29, 2007 | Issued |
Array
(
[id] => 177815
[patent_doc_number] => 07655523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Advanced CMOS using super steep retrograde wells'
[patent_app_type] => utility
[patent_app_number] => 11/928652
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3518
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/655/07655523.pdf
[firstpage_image] =>[orig_patent_app_number] => 11928652
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/928652 | Advanced CMOS using super steep retrograde wells | Oct 29, 2007 | Issued |
Array
(
[id] => 4829319
[patent_doc_number] => 20080128824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'Semiconductor Device and Method for Manufacturing Thereof'
[patent_app_type] => utility
[patent_app_number] => 11/929840
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2021
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20080128824.pdf
[firstpage_image] =>[orig_patent_app_number] => 11929840
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/929840 | Semiconductor Device and Method for Manufacturing Thereof | Oct 29, 2007 | Abandoned |
Array
(
[id] => 4879836
[patent_doc_number] => 20080153219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Method for Manufacturing CMOS Image Sensor'
[patent_app_type] => utility
[patent_app_number] => 11/929960
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1781
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20080153219.pdf
[firstpage_image] =>[orig_patent_app_number] => 11929960
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/929960 | Method for Manufacturing CMOS Image Sensor | Oct 29, 2007 | Abandoned |
Array
(
[id] => 4901786
[patent_doc_number] => 20080111198
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'Stacked semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/978330
[patent_app_country] => US
[patent_app_date] => 2007-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9620
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20080111198.pdf
[firstpage_image] =>[orig_patent_app_number] => 11978330
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/978330 | Stacked semiconductor device and method of manufacturing the same | Oct 28, 2007 | Abandoned |
Array
(
[id] => 4899416
[patent_doc_number] => 20080119030
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-22
[patent_title] => 'Method for manufacturing thin film semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/976820
[patent_app_country] => US
[patent_app_date] => 2007-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9505
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20080119030.pdf
[firstpage_image] =>[orig_patent_app_number] => 11976820
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976820 | Method for manufacturing thin film semiconductor device | Oct 28, 2007 | Abandoned |
Array
(
[id] => 4899413
[patent_doc_number] => 20080119027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-22
[patent_title] => 'VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION'
[patent_app_type] => utility
[patent_app_number] => 11/925723
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 14466
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20080119027.pdf
[firstpage_image] =>[orig_patent_app_number] => 11925723
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/925723 | Vertically stacked field programmable nonvolatile memory and method of fabrication | Oct 25, 2007 | Issued |
Array
(
[id] => 4893459
[patent_doc_number] => 20080102557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-01
[patent_title] => 'Method of forming an isolation layer and method of manufacturing an image device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/976660
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5134
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20080102557.pdf
[firstpage_image] =>[orig_patent_app_number] => 11976660
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976660 | Method of forming an isolation layer and method of manufacturing an image device using the same | Oct 25, 2007 | Abandoned |
Array
(
[id] => 4576602
[patent_doc_number] => 07829945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Lateral diffusion field effect transistor with asymmetric gate dielectric profile'
[patent_app_type] => utility
[patent_app_number] => 11/924650
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 7384
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/829/07829945.pdf
[firstpage_image] =>[orig_patent_app_number] => 11924650
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/924650 | Lateral diffusion field effect transistor with asymmetric gate dielectric profile | Oct 25, 2007 | Issued |