
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5016294
[patent_doc_number] => 20070259503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-08
[patent_title] => 'METHOD OF FABRICATING A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/777291
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/777291 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE | Jul 12, 2007 | Abandoned |
Array
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[id] => 5310303
[patent_doc_number] => 20090017584
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[patent_kind] => A1
[patent_issue_date] => 2009-01-15
[patent_title] => 'PROCESS FOR FINFET SPACER FORMATION'
[patent_app_type] => utility
[patent_app_number] => 11/776710
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[patent_app_date] => 2007-07-12
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[firstpage_image] =>[orig_patent_app_number] => 11776710
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/776710 | Process for finFET spacer formation | Jul 11, 2007 | Issued |
Array
(
[id] => 5310282
[patent_doc_number] => 20090017563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-15
[patent_title] => 'PLASMA TREATMENT AND REPAIR PROCESSES FOR REDUCING SIDEWALL DAMAGE IN LOW-K DIELECTRICS'
[patent_app_type] => utility
[patent_app_number] => 11/776130
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[patent_app_date] => 2007-07-11
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[firstpage_image] =>[orig_patent_app_number] => 11776130
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/776130 | Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics | Jul 10, 2007 | Issued |
Array
(
[id] => 5008072
[patent_doc_number] => 20070278549
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[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'Integrated Circuit with a Transistor Structure Element'
[patent_app_type] => utility
[patent_app_number] => 11/775719
[patent_app_country] => US
[patent_app_date] => 2007-07-10
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Array
(
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[patent_title] => 'ESD PROTECTION CIRCUIT FOR SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/775460 | ESD protection circuit for semiconductor device | Jul 9, 2007 | Issued |
Array
(
[id] => 4803169
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[patent_title] => 'Leadframes for Improved Moisture Reliability and Enhanced Solderability of Semiconductor Devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/774914 | Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices | Jul 8, 2007 | Issued |
Array
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[patent_title] => 'Method for Fabricating Semiconductor Device'
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/773180 | Method for Fabricating Semiconductor Device | Jul 2, 2007 | Abandoned |
Array
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[id] => 4922060
[patent_doc_number] => 20080070375
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[patent_issue_date] => 2008-03-20
[patent_title] => 'Method for Fabricating a Storage Electrode of a Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 11/770980
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[patent_app_date] => 2007-06-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/770980 | Method for fabricating a storage electrode of a semiconductor device | Jun 28, 2007 | Issued |
Array
(
[id] => 5014112
[patent_doc_number] => 20070257320
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[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
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[patent_app_number] => 11/771617
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/771617 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Jun 28, 2007 | Abandoned |
Array
(
[id] => 583256
[patent_doc_number] => 07445981
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-11-04
[patent_title] => 'Method for forming a dual metal gate structure'
[patent_app_type] => utility
[patent_app_number] => 11/771690
[patent_app_country] => US
[patent_app_date] => 2007-06-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/771690 | Method for forming a dual metal gate structure | Jun 28, 2007 | Issued |
Array
(
[id] => 141928
[patent_doc_number] => 07691713
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[patent_title] => 'Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film'
[patent_app_type] => utility
[patent_app_number] => 11/767734
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Array
(
[id] => 5210522
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[patent_title] => 'Semiconductor device and method of manufacturing the same'
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Array
(
[id] => 5199279
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[patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DOPED SILICON FILM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/765145 | Method for manufacturing a semiconductor device having a doped silicon film | Jun 18, 2007 | Issued |
Array
(
[id] => 4800424
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[patent_issue_date] => 2008-01-17
[patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/764560 | Thin film transistor array panel and method of manufacture | Jun 17, 2007 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/763480 | Light-emitting diode arrays and methods of manufacture | Jun 14, 2007 | Issued |
Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/808228 | Semiconductor memory device and method for producing the same | Jun 6, 2007 | Issued |