David Vu

Array ( [id] => 169610 [patent_doc_number] => 07667261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Split-gate memory cells and fabrication methods thereof' [patent_app_type] => utility [patent_app_number] => 11/785382 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 44 [patent_no_of_words] => 5823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/667/07667261.pdf [firstpage_image] =>[orig_patent_app_number] => 11785382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5175170 [patent_doc_number] => 20070176228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/733993 [patent_app_country] => US [patent_app_date] => 2007-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4733 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176228.pdf [firstpage_image] =>[orig_patent_app_number] => 11733993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5126045 [patent_doc_number] => 20070238316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A NITROGEN-CONTAINING GATE INSULATING FILM' [patent_app_type] => utility [patent_app_number] => 11/697050 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4043 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20070238316.pdf [firstpage_image] =>[orig_patent_app_number] => 11697050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5225158 [patent_doc_number] => 20070254424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Method for fabricating CMOS image sensor with plasma damage-free photodiode' [patent_app_type] => utility [patent_app_number] => 11/727750 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3302 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20070254424.pdf [firstpage_image] =>[orig_patent_app_number] => 11727750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5217324 [patent_doc_number] => 20070158635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Semiconductor memory device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/724209 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4831 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158635.pdf [firstpage_image] =>[orig_patent_app_number] => 11724209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5026233 [patent_doc_number] => 20070267679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Nonvolatile memory devices including floating gates formed of silicon nano-crystals and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/723020 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4559 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267679.pdf [firstpage_image] =>[orig_patent_app_number] => 11723020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5219931 [patent_doc_number] => 20070161242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Semiconductor device having copper wiring' [patent_app_type] => utility [patent_app_number] => 11/714886 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3691 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20070161242.pdf [firstpage_image] =>[orig_patent_app_number] => 11714886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4963124 [patent_doc_number] => 20080105944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Crosstalk Improvement Through P on N Structure For Image Sensor' [patent_app_type] => utility [patent_app_number] => 11/682350 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3654 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20080105944.pdf [firstpage_image] =>[orig_patent_app_number] => 11682350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 170524 [patent_doc_number] => 07662675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Method of forming metal thin film and metal wiring pattern and method of manufacturing display panel' [patent_app_type] => utility [patent_app_number] => 11/682420 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 8533 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/662/07662675.pdf [firstpage_image] =>[orig_patent_app_number] => 11682420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5256747 [patent_doc_number] => 20070210379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/713620 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18514 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210379.pdf [firstpage_image] =>[orig_patent_app_number] => 11713620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5186031 [patent_doc_number] => 20070164338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Method of forming nano-sized MTJ cell without contact hole' [patent_app_type] => utility [patent_app_number] => 11/710475 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3130 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164338.pdf [firstpage_image] =>[orig_patent_app_number] => 11710475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9504262 [patent_doc_number] => 08742580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Method of wire bonding over active area of a semiconductor circuit' [patent_app_type] => utility [patent_app_number] => 11/678600 [patent_app_country] => US [patent_app_date] => 2007-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4431 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11678600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 142591 [patent_doc_number] => 07687828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Field-effect transistor' [patent_app_type] => utility [patent_app_number] => 11/709690 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5423 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687828.pdf [firstpage_image] =>[orig_patent_app_number] => 11709690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5113024 [patent_doc_number] => 20070196939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method of manufacturing light emitting diode package' [patent_app_type] => utility [patent_app_number] => 11/709130 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2928 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20070196939.pdf [firstpage_image] =>[orig_patent_app_number] => 11709130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4870686 [patent_doc_number] => 20080197420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Method for fabricating dual-gate semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/707490 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5658 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197420.pdf [firstpage_image] =>[orig_patent_app_number] => 11707490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 236542 [patent_doc_number] => 07595523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Gate pullback at ends of high-voltage vertical transistor structure' [patent_app_type] => utility [patent_app_number] => 11/707820 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 5376 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595523.pdf [firstpage_image] =>[orig_patent_app_number] => 11707820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 228767 [patent_doc_number] => 07601580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Image sensor and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/706370 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4632 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/601/07601580.pdf [firstpage_image] =>[orig_patent_app_number] => 11706370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5069581 [patent_doc_number] => 20070190683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'PHASE CHANGEABLE STRUCTURE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/674580 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5190 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190683.pdf [firstpage_image] =>[orig_patent_app_number] => 11674580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 322505 [patent_doc_number] => 07517737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Structures for and method of silicide formation on memory array and peripheral logic devices' [patent_app_type] => utility [patent_app_number] => 11/672150 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7558 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517737.pdf [firstpage_image] =>[orig_patent_app_number] => 11672150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4619670 [patent_doc_number] => 07999391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Multilayered wiring structure, and method for manufacturing multilayered wiring' [patent_app_type] => utility [patent_app_number] => 12/278339 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7938 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/999/07999391.pdf [firstpage_image] =>[orig_patent_app_number] => 12278339 [rel_patent_id] =>[rel_patent_doc_number] =>)