Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6448196 [patent_doc_number] => 20100038775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'MINIATURE ELECTRONIC COMPONENT FOR MICROWAVE APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/722306 [patent_app_country] => US [patent_app_date] => 2005-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3338 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20100038775.pdf [firstpage_image] =>[orig_patent_app_number] => 11722306 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/722306
Miniature electronic component for microwave applications Dec 6, 2005 Issued
Array ( [id] => 5713272 [patent_doc_number] => 20060076635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies' [patent_app_type] => utility [patent_app_number] => 11/295177 [patent_app_country] => US [patent_app_date] => 2005-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6066 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076635.pdf [firstpage_image] =>[orig_patent_app_number] => 11295177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295177
Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies Dec 4, 2005 Issued
Array ( [id] => 5715698 [patent_doc_number] => 20060079061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film' [patent_app_type] => utility [patent_app_number] => 11/292360 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 11117 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20060079061.pdf [firstpage_image] =>[orig_patent_app_number] => 11292360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/292360
Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film Dec 1, 2005 Issued
Array ( [id] => 5713242 [patent_doc_number] => 20060076605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'IMPROVED FLASH FORWARD TUNNELING VOLTAGE (FTV) FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/287856 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076605.pdf [firstpage_image] =>[orig_patent_app_number] => 11287856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/287856
IMPROVED FLASH FORWARD TUNNELING VOLTAGE (FTV) FLASH MEMORY DEVICE Nov 27, 2005 Abandoned
Array ( [id] => 5718488 [patent_doc_number] => 20060071261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Integrated semiconductor storage with at least a storage cell and procedure' [patent_app_type] => utility [patent_app_number] => 11/283804 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9544 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071261.pdf [firstpage_image] =>[orig_patent_app_number] => 11283804 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/283804
Integrated semiconductor storage with at least a storage cell and procedure Nov 21, 2005 Issued
Array ( [id] => 5649159 [patent_doc_number] => 20060134894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Method of manufacturing polycrystalline Si film and manufacturing stacked transistor using the same' [patent_app_type] => utility [patent_app_number] => 11/283874 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2173 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134894.pdf [firstpage_image] =>[orig_patent_app_number] => 11283874 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/283874
Method of manufacturing a stacked transistor having a polycrystalline Si film Nov 21, 2005 Issued
Array ( [id] => 5823721 [patent_doc_number] => 20060060903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor device including a TCAM having a storage element formed with a DRAM' [patent_app_type] => utility [patent_app_number] => 11/274299 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5844 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060903.pdf [firstpage_image] =>[orig_patent_app_number] => 11274299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274299
Semiconductor device including a TCAM having a storage element formed with a DRAM Nov 15, 2005 Issued
Array ( [id] => 5773886 [patent_doc_number] => 20060102900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Flat panel display and its method of fabrication' [patent_app_type] => utility [patent_app_number] => 11/274190 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20060102900.pdf [firstpage_image] =>[orig_patent_app_number] => 11274190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274190
Flat panel display and its method of fabrication Nov 15, 2005 Abandoned
Array ( [id] => 5637597 [patent_doc_number] => 20060068570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Structure with through hole, production method thereof, and liquid discharge head' [patent_app_type] => utility [patent_app_number] => 11/272869 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7576 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20060068570.pdf [firstpage_image] =>[orig_patent_app_number] => 11272869 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/272869
Structure with through hole, production method thereof, and liquid discharge head Nov 14, 2005 Issued
Array ( [id] => 5634947 [patent_doc_number] => 20060065920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Semiconductor memory device and method for producing the same' [patent_app_type] => utility [patent_app_number] => 11/271739 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13084 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20060065920.pdf [firstpage_image] =>[orig_patent_app_number] => 11271739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271739
Semiconductor memory device and method for producing the same Nov 13, 2005 Issued
Array ( [id] => 425430 [patent_doc_number] => 07271413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/274727 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 7725 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271413.pdf [firstpage_image] =>[orig_patent_app_number] => 11274727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274727
Semiconductor constructions Nov 13, 2005 Issued
Array ( [id] => 448543 [patent_doc_number] => 07250344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology' [patent_app_type] => utility [patent_app_number] => 11/272260 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2351 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250344.pdf [firstpage_image] =>[orig_patent_app_number] => 11272260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/272260
Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology Nov 9, 2005 Issued
Array ( [id] => 861298 [patent_doc_number] => 07372102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology' [patent_app_type] => utility [patent_app_number] => 11/272259 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2340 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372102.pdf [firstpage_image] =>[orig_patent_app_number] => 11272259 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/272259
Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology Nov 9, 2005 Issued
Array ( [id] => 228775 [patent_doc_number] => 07601588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same' [patent_app_type] => utility [patent_app_number] => 11/267360 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8582 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/601/07601588.pdf [firstpage_image] =>[orig_patent_app_number] => 11267360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267360
Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same Nov 3, 2005 Issued
Array ( [id] => 5034787 [patent_doc_number] => 20070099326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'eFuse and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/266740 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099326.pdf [firstpage_image] =>[orig_patent_app_number] => 11266740 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266740
eFuse and methods of manufacturing the same Nov 2, 2005 Issued
Array ( [id] => 5713211 [patent_doc_number] => 20060076574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Gallium-nitride based light-emitting diodes structure with high reverse withstanding voltage and anti-ESD capability' [patent_app_type] => utility [patent_app_number] => 11/266415 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2282 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076574.pdf [firstpage_image] =>[orig_patent_app_number] => 11266415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266415
Gallium-nitride based light-emitting diodes structure with high reverse withstanding voltage and anti-ESD capability Nov 2, 2005 Abandoned
Array ( [id] => 4634421 [patent_doc_number] => 08012872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Planarising damascene structures' [patent_app_type] => utility [patent_app_number] => 11/718876 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4635 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/012/08012872.pdf [firstpage_image] =>[orig_patent_app_number] => 11718876 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/718876
Planarising damascene structures Nov 1, 2005 Issued
Array ( [id] => 5807873 [patent_doc_number] => 20060094228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/259547 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2973 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20060094228.pdf [firstpage_image] =>[orig_patent_app_number] => 11259547 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/259547
Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits Oct 25, 2005 Abandoned
Array ( [id] => 5898233 [patent_doc_number] => 20060043466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Stepped gate configuration for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/257636 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043466.pdf [firstpage_image] =>[orig_patent_app_number] => 11257636 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257636
Stepped gate configuration for non-volatile memory Oct 24, 2005 Issued
Array ( [id] => 5898234 [patent_doc_number] => 20060043467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Stepped gate configuration for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/257637 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043467.pdf [firstpage_image] =>[orig_patent_app_number] => 11257637 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257637
Stepped gate configuration for non-volatile memory Oct 24, 2005 Issued
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