Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 474025 [patent_doc_number] => 07230301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Single-crystal silicon semiconductor structure' [patent_app_type] => utility [patent_app_number] => 10/884910 [patent_app_country] => US [patent_app_date] => 2004-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 4866 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230301.pdf [firstpage_image] =>[orig_patent_app_number] => 10884910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884910
Single-crystal silicon semiconductor structure Jul 5, 2004 Issued
Array ( [id] => 493514 [patent_doc_number] => 07211480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Semiconductor device with shallow trench isolation and its manufacture method' [patent_app_type] => utility [patent_app_number] => 10/882260 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 4963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/211/07211480.pdf [firstpage_image] =>[orig_patent_app_number] => 10882260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882260
Semiconductor device with shallow trench isolation and its manufacture method Jul 1, 2004 Issued
Array ( [id] => 7264059 [patent_doc_number] => 20040241937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Gate with dual gate dielectric layer and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/884769 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1947 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241937.pdf [firstpage_image] =>[orig_patent_app_number] => 10884769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884769
Gate with dual gate dielectric layer and method of fabricating the same Jul 1, 2004 Issued
Array ( [id] => 7031931 [patent_doc_number] => 20050030440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Thin film transistor array panel and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/884083 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6832 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030440.pdf [firstpage_image] =>[orig_patent_app_number] => 10884083 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884083
Thin film transistor array panel and manufacturing method thereof Jun 30, 2004 Issued
Array ( [id] => 737096 [patent_doc_number] => 07033872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Thin film transistor and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/884500 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4553 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/033/07033872.pdf [firstpage_image] =>[orig_patent_app_number] => 10884500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884500
Thin film transistor and method of fabricating the same Jun 30, 2004 Issued
Array ( [id] => 521601 [patent_doc_number] => 07186617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Methods of forming integrated circuit devices having a resistor pattern and plug pattern that are made from a same material' [patent_app_type] => utility [patent_app_number] => 10/880919 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 6405 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/186/07186617.pdf [firstpage_image] =>[orig_patent_app_number] => 10880919 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880919
Methods of forming integrated circuit devices having a resistor pattern and plug pattern that are made from a same material Jun 29, 2004 Issued
Array ( [id] => 5894989 [patent_doc_number] => 20060003528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Flash memory with metal-insulator-metal tunneling program and erase' [patent_app_type] => utility [patent_app_number] => 10/881662 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4783 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003528.pdf [firstpage_image] =>[orig_patent_app_number] => 10881662 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881662
Flash memory with metal-insulator-metal tunneling program and erase Jun 29, 2004 Issued
Array ( [id] => 5895059 [patent_doc_number] => 20060003598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Gradient low k material' [patent_app_type] => utility [patent_app_number] => 10/881700 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3159 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003598.pdf [firstpage_image] =>[orig_patent_app_number] => 10881700 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881700
Gradient low k material Jun 29, 2004 Issued
Array ( [id] => 7274318 [patent_doc_number] => 20040233769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor memory cell and method of forming same' [patent_app_type] => new [patent_app_number] => 10/876461 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5076 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233769.pdf [firstpage_image] =>[orig_patent_app_number] => 10876461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876461
Semiconductor memory cell and method of forming same Jun 27, 2004 Issued
Array ( [id] => 7235344 [patent_doc_number] => 20050139821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Organic electroluminescent display device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/876690 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5495 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139821.pdf [firstpage_image] =>[orig_patent_app_number] => 10876690 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876690
Organic electroluminescent display device and method of fabricating the same Jun 27, 2004 Issued
Array ( [id] => 7083379 [patent_doc_number] => 20050048759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method for fabricating thermally enhanced semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/876469 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3950 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20050048759.pdf [firstpage_image] =>[orig_patent_app_number] => 10876469 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876469
Method for fabricating thermally enhanced semiconductor device Jun 27, 2004 Issued
Array ( [id] => 6975463 [patent_doc_number] => 20050285178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Formation of memory cells and select gates of NAND memory arrays' [patent_app_type] => utility [patent_app_number] => 10/878799 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4698 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285178.pdf [firstpage_image] =>[orig_patent_app_number] => 10878799 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878799
Formation of memory cells and select gates of NAND memory arrays Jun 27, 2004 Issued
Array ( [id] => 7061253 [patent_doc_number] => 20050003614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Semiconductor memory device including a flash memory cell array and a mask read-only memory cell array' [patent_app_type] => utility [patent_app_number] => 10/875720 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20050003614.pdf [firstpage_image] =>[orig_patent_app_number] => 10875720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875720
Semiconductor memory device including a flash memory cell array and a mask read-only memory cell array Jun 24, 2004 Issued
Array ( [id] => 7154810 [patent_doc_number] => 20050026419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Method of forming multilayer interconnection structure, and manufacturing method for multilayer wiring boards' [patent_app_type] => utility [patent_app_number] => 10/875590 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026419.pdf [firstpage_image] =>[orig_patent_app_number] => 10875590 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875590
Method of forming multilayer interconnection structure, and manufacturing method for multilayer wiring boards Jun 24, 2004 Issued
Array ( [id] => 6977968 [patent_doc_number] => 20050287686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method to improve water-barrier performance by changing film surface morphology' [patent_app_type] => utility [patent_app_number] => 10/876440 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5160 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287686.pdf [firstpage_image] =>[orig_patent_app_number] => 10876440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876440
Method to improve water-barrier performance by changing film surface morphology Jun 24, 2004 Issued
Array ( [id] => 6978022 [patent_doc_number] => 20050287740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'System and method of forming a split-gate flash memory cell' [patent_app_type] => utility [patent_app_number] => 10/875429 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2550 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287740.pdf [firstpage_image] =>[orig_patent_app_number] => 10875429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875429
System and method of forming a split-gate flash memory cell Jun 23, 2004 Abandoned
Array ( [id] => 884317 [patent_doc_number] => 07351606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Method for forming a bottom gate thin film transistor using a blend solution to form a semiconducting layer and an insulating layer' [patent_app_type] => utility [patent_app_number] => 10/876229 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3475 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/351/07351606.pdf [firstpage_image] =>[orig_patent_app_number] => 10876229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876229
Method for forming a bottom gate thin film transistor using a blend solution to form a semiconducting layer and an insulating layer Jun 23, 2004 Issued
Array ( [id] => 701508 [patent_doc_number] => 07064042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-20 [patent_title] => 'Self aligned compact bipolar junction transistor layout, and method of making same' [patent_app_type] => utility [patent_app_number] => 10/877749 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3489 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064042.pdf [firstpage_image] =>[orig_patent_app_number] => 10877749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877749
Self aligned compact bipolar junction transistor layout, and method of making same Jun 23, 2004 Issued
Array ( [id] => 348773 [patent_doc_number] => 07494888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Device and method using isotopically enriched silicon' [patent_app_type] => utility [patent_app_number] => 10/875029 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494888.pdf [firstpage_image] =>[orig_patent_app_number] => 10875029 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875029
Device and method using isotopically enriched silicon Jun 22, 2004 Issued
Array ( [id] => 7275787 [patent_doc_number] => 20040235238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Multi-layer integrated circuit capacitor electrodes and methods of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/873546 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8750 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20040235238.pdf [firstpage_image] =>[orig_patent_app_number] => 10873546 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/873546
Methods of manufacturing multi-layer integrated circuit capacitor electrodes Jun 21, 2004 Issued
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