
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7114352
[patent_doc_number] => 20050067652
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Nonvolatile semiconductor memory and a fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/868806
[patent_app_country] => US
[patent_app_date] => 2004-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[pdf_file] => publications/A1/0067/20050067652.pdf
[firstpage_image] =>[orig_patent_app_number] => 10868806
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/868806 | Nonvolatile semiconductor memory and a fabrication method thereof | Jun 16, 2004 | Issued |
Array
(
[id] => 662739
[patent_doc_number] => 07101777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'Methods for manufacturing stacked gate structure and field effect transistor provided with the same'
[patent_app_type] => utility
[patent_app_number] => 10/864320
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[patent_app_date] => 2004-06-10
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[pdf_file] => patents/07/101/07101777.pdf
[firstpage_image] =>[orig_patent_app_number] => 10864320
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/864320 | Methods for manufacturing stacked gate structure and field effect transistor provided with the same | Jun 9, 2004 | Issued |
Array
(
[id] => 7086569
[patent_doc_number] => 20050006681
[patent_country] => US
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[patent_issue_date] => 2005-01-13
[patent_title] => 'Semiconductor memory device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/863330
[patent_app_country] => US
[patent_app_date] => 2004-06-09
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[firstpage_image] =>[orig_patent_app_number] => 10863330
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/863330 | Semiconductor memory device and method for fabricating the same | Jun 8, 2004 | Issued |
Array
(
[id] => 582195
[patent_doc_number] => 07449408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/863170
[patent_app_country] => US
[patent_app_date] => 2004-06-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/449/07449408.pdf
[firstpage_image] =>[orig_patent_app_number] => 10863170
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/863170 | Method for manufacturing semiconductor device | Jun 7, 2004 | Issued |
Array
(
[id] => 7375665
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[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 10/861450
[patent_app_country] => US
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[pdf_file] => publications/A1/0219/20040219727.pdf
[firstpage_image] =>[orig_patent_app_number] => 10861450
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/861450 | Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device | Jun 6, 2004 | Abandoned |
Array
(
[id] => 703158
[patent_doc_number] => 07064427
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Buried array capacitor and microelectronic structure incorporating the same'
[patent_app_type] => utility
[patent_app_number] => 10/863700
[patent_app_country] => US
[patent_app_date] => 2004-06-07
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[pdf_file] => patents/07/064/07064427.pdf
[firstpage_image] =>[orig_patent_app_number] => 10863700
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/863700 | Buried array capacitor and microelectronic structure incorporating the same | Jun 6, 2004 | Issued |
Array
(
[id] => 7423514
[patent_doc_number] => 20040229425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'Semiconductor device and bump formation method'
[patent_app_type] => new
[patent_app_number] => 10/862079
[patent_app_country] => US
[patent_app_date] => 2004-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4890
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[pdf_file] => publications/A1/0229/20040229425.pdf
[firstpage_image] =>[orig_patent_app_number] => 10862079
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/862079 | Semiconductor device and bump formation method | Jun 6, 2004 | Abandoned |
Array
(
[id] => 535438
[patent_doc_number] => 07180116
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-20
[patent_title] => 'Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor'
[patent_app_type] => utility
[patent_app_number] => 10/861148
[patent_app_country] => US
[patent_app_date] => 2004-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3095
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[pdf_file] => patents/07/180/07180116.pdf
[firstpage_image] =>[orig_patent_app_number] => 10861148
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/861148 | Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor | Jun 3, 2004 | Issued |
Array
(
[id] => 557500
[patent_doc_number] => 07157367
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-02
[patent_title] => 'Device structure having enhanced surface adhesion and failure mode analysis'
[patent_app_type] => utility
[patent_app_number] => 10/861149
[patent_app_country] => US
[patent_app_date] => 2004-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/07/157/07157367.pdf
[firstpage_image] =>[orig_patent_app_number] => 10861149
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/861149 | Device structure having enhanced surface adhesion and failure mode analysis | Jun 3, 2004 | Issued |
Array
(
[id] => 7429126
[patent_doc_number] => 20040266060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Cost-reducing and process-simplifying wiring board and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/859639
[patent_app_country] => US
[patent_app_date] => 2004-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 4627
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[pdf_file] => publications/A1/0266/20040266060.pdf
[firstpage_image] =>[orig_patent_app_number] => 10859639
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/859639 | Cost-reducing and process-simplifying wiring board and manufacturing method thereof | Jun 2, 2004 | Issued |
Array
(
[id] => 687710
[patent_doc_number] => 07078736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-18
[patent_title] => 'Light emitting device with a photonic crystal'
[patent_app_type] => utility
[patent_app_number] => 10/856210
[patent_app_country] => US
[patent_app_date] => 2004-05-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/078/07078736.pdf
[firstpage_image] =>[orig_patent_app_number] => 10856210
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/856210 | Light emitting device with a photonic crystal | May 26, 2004 | Issued |
Array
(
[id] => 7053830
[patent_doc_number] => 20050275002
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Vertical split gate memory cell and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/854711
[patent_app_country] => US
[patent_app_date] => 2004-05-27
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[pdf_file] => publications/A1/0275/20050275002.pdf
[firstpage_image] =>[orig_patent_app_number] => 10854711
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/854711 | Vertical split gate memory cell and manufacturing method thereof | May 26, 2004 | Issued |
Array
(
[id] => 7206117
[patent_doc_number] => 20050258470
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Gate stack of nanocrystal memory and method for forming same'
[patent_app_type] => utility
[patent_app_number] => 10/850897
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10850897
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/850897 | Gate stack of nanocrystal memory and method for forming same | May 19, 2004 | Abandoned |
Array
(
[id] => 717090
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[patent_country] => US
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[patent_issue_date] => 2006-05-30
[patent_title] => 'Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card'
[patent_app_type] => utility
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[pdf_file] => patents/07/053/07053437.pdf
[firstpage_image] =>[orig_patent_app_number] => 10848214
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/848214 | Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card | May 18, 2004 | Issued |
Array
(
[id] => 790841
[patent_doc_number] => 06984865
[patent_country] => US
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[patent_issue_date] => 2006-01-10
[patent_title] => 'Magnetic random access memory'
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[pdf_file] => patents/06/984/06984865.pdf
[firstpage_image] =>[orig_patent_app_number] => 10847384
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/847384 | Magnetic random access memory | May 17, 2004 | Issued |
Array
(
[id] => 7250141
[patent_doc_number] => 20040238905
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[patent_issue_date] => 2004-12-02
[patent_title] => 'Novel gate dielectric structure for reducing boron penetration and current leakage'
[patent_app_type] => new
[patent_app_number] => 10/847789
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/847789 | Gate dielectric structure for reducing boron penetration and current leakage | May 17, 2004 | Issued |
Array
(
[id] => 779550
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[patent_country] => US
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[patent_title] => 'Integrated semiconductor storage with at least a storage cell and procedure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/840328 | Integrated semiconductor storage with at least a storage cell and procedure | May 6, 2004 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834840 | Overvoltage protection device and manufacturing process for the same | Apr 29, 2004 | Issued |
Array
(
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[patent_title] => 'Method for manufacturing semiconductor device having trench gate'
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[firstpage_image] =>[orig_patent_app_number] => 10834029
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834029 | Method for manufacturing semiconductor device having trench gate | Apr 28, 2004 | Abandoned |
Array
(
[id] => 7375909
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[patent_title] => 'Method for forming conductive bump and device formed with such a conductive bump'
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[firstpage_image] =>[orig_patent_app_number] => 10833150
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/833150 | Method for forming conductive bump and device formed with such a conductive bump | Apr 27, 2004 | Abandoned |