
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6926019
[patent_doc_number] => 20050239274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-27
[patent_title] => 'Method for growth of group III-V semiconductor material on a dielectric'
[patent_app_type] => utility
[patent_app_number] => 10/830729
[patent_app_country] => US
[patent_app_date] => 2004-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1510
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20050239274.pdf
[firstpage_image] =>[orig_patent_app_number] => 10830729
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/830729 | Method for growth of group III-V semiconductor material on a dielectric | Apr 22, 2004 | Issued |
Array
(
[id] => 627002
[patent_doc_number] => 07135385
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-11-14
[patent_title] => 'Semiconductor devices having a back surface protective coating'
[patent_app_type] => utility
[patent_app_number] => 10/830820
[patent_app_country] => US
[patent_app_date] => 2004-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6059
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/135/07135385.pdf
[firstpage_image] =>[orig_patent_app_number] => 10830820
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/830820 | Semiconductor devices having a back surface protective coating | Apr 22, 2004 | Issued |
Array
(
[id] => 7296457
[patent_doc_number] => 20040214381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Process for the production of organic transistor and organic transistor'
[patent_app_type] => new
[patent_app_number] => 10/829179
[patent_app_country] => US
[patent_app_date] => 2004-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2745
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20040214381.pdf
[firstpage_image] =>[orig_patent_app_number] => 10829179
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/829179 | Process for the production of organic transistor and organic transistor | Apr 21, 2004 | Abandoned |
Array
(
[id] => 7430386
[patent_doc_number] => 20040266216
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Method for improving uniformity in deposited low k dielectric material'
[patent_app_type] => new
[patent_app_number] => 10/828030
[patent_app_country] => US
[patent_app_date] => 2004-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2743
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20040266216.pdf
[firstpage_image] =>[orig_patent_app_number] => 10828030
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/828030 | Method for improving uniformity in deposited low k dielectric material | Apr 19, 2004 | Abandoned |
Array
(
[id] => 698811
[patent_doc_number] => 07067348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Method of forming a programmable memory cell and chalcogenide structure'
[patent_app_type] => utility
[patent_app_number] => 10/825319
[patent_app_country] => US
[patent_app_date] => 2004-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2835
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067348.pdf
[firstpage_image] =>[orig_patent_app_number] => 10825319
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/825319 | Method of forming a programmable memory cell and chalcogenide structure | Apr 15, 2004 | Issued |
Array
(
[id] => 7253122
[patent_doc_number] => 20040259343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Composite spacer liner for improved transistor performance'
[patent_app_type] => new
[patent_app_number] => 10/824428
[patent_app_country] => US
[patent_app_date] => 2004-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2816
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20040259343.pdf
[firstpage_image] =>[orig_patent_app_number] => 10824428
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/824428 | Composite spacer liner for improved transistor performance | Apr 14, 2004 | Issued |
Array
(
[id] => 7061215
[patent_doc_number] => 20050003576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Semiconductor device manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 10/824639
[patent_app_country] => US
[patent_app_date] => 2004-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2173
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20050003576.pdf
[firstpage_image] =>[orig_patent_app_number] => 10824639
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/824639 | Semiconductor device manufacturing method | Apr 14, 2004 | Issued |
Array
(
[id] => 7154853
[patent_doc_number] => 20050026439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Semiconductor device fabrication method'
[patent_app_type] => utility
[patent_app_number] => 10/823729
[patent_app_country] => US
[patent_app_date] => 2004-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 57
[patent_figures_cnt] => 57
[patent_no_of_words] => 23985
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20050026439.pdf
[firstpage_image] =>[orig_patent_app_number] => 10823729
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/823729 | Semiconductor device fabrication method | Apr 13, 2004 | Issued |
Array
(
[id] => 7080595
[patent_doc_number] => 20050045975
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Solid state imaging device with inner lens and manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 10/823660
[patent_app_country] => US
[patent_app_date] => 2004-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6716
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20050045975.pdf
[firstpage_image] =>[orig_patent_app_number] => 10823660
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/823660 | Solid state imaging device with inner lens and manufacture thereof | Apr 13, 2004 | Issued |
Array
(
[id] => 7429043
[patent_doc_number] => 20040209414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Two position anneal chamber'
[patent_app_type] => new
[patent_app_number] => 10/823849
[patent_app_country] => US
[patent_app_date] => 2004-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7051
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20040209414.pdf
[firstpage_image] =>[orig_patent_app_number] => 10823849
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/823849 | Two position anneal chamber | Apr 12, 2004 | Issued |
Array
(
[id] => 7122512
[patent_doc_number] => 20050014341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Method of fabricating complementary bipolar transistors with SiGe base regions'
[patent_app_type] => utility
[patent_app_number] => 10/822078
[patent_app_country] => US
[patent_app_date] => 2004-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2117
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20050014341.pdf
[firstpage_image] =>[orig_patent_app_number] => 10822078
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/822078 | Method of fabricating complementary bipolar transistors with SiGe base regions | Apr 7, 2004 | Issued |
Array
(
[id] => 7344136
[patent_doc_number] => 20040191991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Semiconductor integrated circuit and method for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/820128
[patent_app_country] => US
[patent_app_date] => 2004-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 11300
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20040191991.pdf
[firstpage_image] =>[orig_patent_app_number] => 10820128
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/820128 | Semiconductor integrated circuit and method for manufacturing the same | Apr 7, 2004 | Abandoned |
Array
(
[id] => 6952392
[patent_doc_number] => 20050227487
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon'
[patent_app_type] => utility
[patent_app_number] => 10/822118
[patent_app_country] => US
[patent_app_date] => 2004-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3991
[patent_no_of_claims] => 114
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0227/20050227487.pdf
[firstpage_image] =>[orig_patent_app_number] => 10822118
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/822118 | Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon | Apr 7, 2004 | Issued |
Array
(
[id] => 6952342
[patent_doc_number] => 20050227437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Method of forming ONO-type sidewall with reduced bird\'s beak'
[patent_app_type] => utility
[patent_app_number] => 10/821100
[patent_app_country] => US
[patent_app_date] => 2004-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10060
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0227/20050227437.pdf
[firstpage_image] =>[orig_patent_app_number] => 10821100
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821100 | Method of forming ONO-type sidewall with reduced bird's beak | Apr 6, 2004 | Issued |
Array
(
[id] => 7344133
[patent_doc_number] => 20040191990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line'
[patent_app_type] => new
[patent_app_number] => 10/818590
[patent_app_country] => US
[patent_app_date] => 2004-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 10126
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20040191990.pdf
[firstpage_image] =>[orig_patent_app_number] => 10818590
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/818590 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line | Apr 4, 2004 | Issued |
Array
(
[id] => 701424
[patent_doc_number] => 07063998
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Image sensor having photo diode and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/806489
[patent_app_country] => US
[patent_app_date] => 2004-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 3776
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/063/07063998.pdf
[firstpage_image] =>[orig_patent_app_number] => 10806489
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/806489 | Image sensor having photo diode and method for manufacturing the same | Mar 22, 2004 | Issued |
Array
(
[id] => 7398060
[patent_doc_number] => 20040174697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Production process of light emitting device'
[patent_app_type] => new
[patent_app_number] => 10/799606
[patent_app_country] => US
[patent_app_date] => 2004-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4001
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20040174697.pdf
[firstpage_image] =>[orig_patent_app_number] => 10799606
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/799606 | Production process of light emitting device | Mar 14, 2004 | Issued |
Array
(
[id] => 463356
[patent_doc_number] => 07238595
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Epitaxial semiconductor deposition methods and structures'
[patent_app_type] => utility
[patent_app_number] => 10/800390
[patent_app_country] => US
[patent_app_date] => 2004-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 12776
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/238/07238595.pdf
[firstpage_image] =>[orig_patent_app_number] => 10800390
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/800390 | Epitaxial semiconductor deposition methods and structures | Mar 11, 2004 | Issued |
Array
(
[id] => 419084
[patent_doc_number] => 07276759
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-02
[patent_title] => 'Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling'
[patent_app_type] => utility
[patent_app_number] => 10/798138
[patent_app_country] => US
[patent_app_date] => 2004-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5627
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/276/07276759.pdf
[firstpage_image] =>[orig_patent_app_number] => 10798138
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/798138 | Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling | Mar 10, 2004 | Issued |
Array
(
[id] => 658171
[patent_doc_number] => 07105433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Method for treating wafer surface'
[patent_app_type] => utility
[patent_app_number] => 10/708425
[patent_app_country] => US
[patent_app_date] => 2004-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 2002
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/105/07105433.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708425
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708425 | Method for treating wafer surface | Mar 1, 2004 | Issued |