Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7296551 [patent_doc_number] => 20040214422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Semiconductor devices, and manufacturing methods, circuit substrates and electronic equipments for the same' [patent_app_type] => new [patent_app_number] => 10/625689 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3939 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20040214422.pdf [firstpage_image] =>[orig_patent_app_number] => 10625689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625689
Semiconductor devices, and manufacturing methods, circuit substrates and electronic equipments for the same Jul 23, 2003 Abandoned
Array ( [id] => 7675169 [patent_doc_number] => 20040126949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Gate electrode of a semiconductor device and method of forming the same' [patent_app_type] => new [patent_app_number] => 10/626096 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20040126949.pdf [firstpage_image] =>[orig_patent_app_number] => 10626096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626096
Gate electrode of a semiconductor device and method of forming the same Jul 22, 2003 Issued
Array ( [id] => 7383636 [patent_doc_number] => 20040029369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Fabrication method of semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/614789 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9008 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20040029369.pdf [firstpage_image] =>[orig_patent_app_number] => 10614789 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614789
Fabrication method of semiconductor integrated circuit device Jul 8, 2003 Issued
Array ( [id] => 7675126 [patent_doc_number] => 20040126992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/614189 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4567 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20040126992.pdf [firstpage_image] =>[orig_patent_app_number] => 10614189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614189
Semiconductor device and a method of manufacturing the same Jul 7, 2003 Issued
Array ( [id] => 7280958 [patent_doc_number] => 20040063335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Haze-free BST films' [patent_app_type] => new [patent_app_number] => 10/614489 [patent_app_country] => US [patent_app_date] => 2003-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3434 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063335.pdf [firstpage_image] =>[orig_patent_app_number] => 10614489 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614489
Haze-free BST films Jul 2, 2003 Issued
Array ( [id] => 7398781 [patent_doc_number] => 20040018675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Nickel plating process having controlled hydrogen concentration' [patent_app_type] => new [patent_app_number] => 10/610999 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4334 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20040018675.pdf [firstpage_image] =>[orig_patent_app_number] => 10610999 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/610999
Nickel plating process having controlled hydrogen concentration Jun 30, 2003 Abandoned
Array ( [id] => 7234974 [patent_doc_number] => 20040157362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Methods of making microelectronic packages including electrically and/or thermally conductive element' [patent_app_type] => new [patent_app_number] => 10/607289 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6853 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157362.pdf [firstpage_image] =>[orig_patent_app_number] => 10607289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/607289
Methods of making microelectronic packages including electrically and/or thermally conductive element Jun 25, 2003 Issued
Array ( [id] => 690508 [patent_doc_number] => 07074693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Plasma spraying for joining silicon parts' [patent_app_type] => utility [patent_app_number] => 10/602299 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 31 [patent_no_of_words] => 7326 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/074/07074693.pdf [firstpage_image] =>[orig_patent_app_number] => 10602299 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602299
Plasma spraying for joining silicon parts Jun 23, 2003 Issued
Array ( [id] => 1056359 [patent_doc_number] => 06855582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'FinFET gate formation using reverse trim and oxide polish' [patent_app_type] => utility [patent_app_number] => 10/459589 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 44 [patent_no_of_words] => 4285 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855582.pdf [firstpage_image] =>[orig_patent_app_number] => 10459589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459589
FinFET gate formation using reverse trim and oxide polish Jun 11, 2003 Issued
Array ( [id] => 6725255 [patent_doc_number] => 20030207567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Metal film pattern and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/454599 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7700 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207567.pdf [firstpage_image] =>[orig_patent_app_number] => 10454599 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454599
Metal film pattern and manufacturing method thereof Jun 4, 2003 Issued
Array ( [id] => 985484 [patent_doc_number] => 06924212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Method for forming a semiconductor' [patent_app_type] => utility [patent_app_number] => 10/453689 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4907 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924212.pdf [firstpage_image] =>[orig_patent_app_number] => 10453689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453689
Method for forming a semiconductor Jun 3, 2003 Issued
Array ( [id] => 6636455 [patent_doc_number] => 20030211722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line' [patent_app_type] => new [patent_app_number] => 10/452096 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3374 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211722.pdf [firstpage_image] =>[orig_patent_app_number] => 10452096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452096
Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line May 29, 2003 Issued
Array ( [id] => 7221781 [patent_doc_number] => 20040072396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Semiconductor electronic device and method of manufacturing thereof' [patent_app_type] => new [patent_app_number] => 10/449749 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2161 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20040072396.pdf [firstpage_image] =>[orig_patent_app_number] => 10449749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449749
Semiconductor electronic device and method of manufacturing thereof May 28, 2003 Abandoned
Array ( [id] => 7269980 [patent_doc_number] => 20040058498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Gate with dual gate dielectric layer and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/443950 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1946 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20040058498.pdf [firstpage_image] =>[orig_patent_app_number] => 10443950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443950
Gate with dual gate dielectric layer and method of fabricating the same May 21, 2003 Abandoned
Array ( [id] => 7159470 [patent_doc_number] => 20040075139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Semiconductor device and fabrication method with etch stop film below active layer' [patent_app_type] => new [patent_app_number] => 10/441040 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075139.pdf [firstpage_image] =>[orig_patent_app_number] => 10441040 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441040
Semiconductor device and fabrication method with etch stop film below active layer May 19, 2003 Issued
Array ( [id] => 6805068 [patent_doc_number] => 20030232462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages and associated methods' [patent_app_type] => new [patent_app_number] => 10/440590 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6599 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20030232462.pdf [firstpage_image] =>[orig_patent_app_number] => 10440590 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440590
Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages and associated methods May 18, 2003 Issued
Array ( [id] => 654573 [patent_doc_number] => 07109092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Method of room temperature covalent bonding' [patent_app_type] => utility [patent_app_number] => 10/440099 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 7284 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109092.pdf [firstpage_image] =>[orig_patent_app_number] => 10440099 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440099
Method of room temperature covalent bonding May 18, 2003 Issued
Array ( [id] => 988139 [patent_doc_number] => 06921694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Method for fabricating floating gate' [patent_app_type] => utility [patent_app_number] => 10/442308 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1449 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921694.pdf [firstpage_image] =>[orig_patent_app_number] => 10442308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442308
Method for fabricating floating gate May 18, 2003 Issued
Array ( [id] => 1136314 [patent_doc_number] => 06784479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Multi-layer integrated circuit capacitor electrodes' [patent_app_type] => B2 [patent_app_number] => 10/435880 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8672 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784479.pdf [firstpage_image] =>[orig_patent_app_number] => 10435880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435880
Multi-layer integrated circuit capacitor electrodes May 11, 2003 Issued
Array ( [id] => 1120868 [patent_doc_number] => 06798029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method of fabricating micro-electromechanical switches on CMOS compatible substrates' [patent_app_type] => B2 [patent_app_number] => 10/434999 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 4334 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798029.pdf [firstpage_image] =>[orig_patent_app_number] => 10434999 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434999
Method of fabricating micro-electromechanical switches on CMOS compatible substrates May 8, 2003 Issued
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