
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 732525
[patent_doc_number] => 07037762
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-02
[patent_title] => 'Phase changeable memory devices having multi-level data storage elements and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/430980
[patent_app_country] => US
[patent_app_date] => 2003-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 5763
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/037/07037762.pdf
[firstpage_image] =>[orig_patent_app_number] => 10430980
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/430980 | Phase changeable memory devices having multi-level data storage elements and methods of fabricating the same | May 6, 2003 | Issued |
Array
(
[id] => 6612363
[patent_doc_number] => 20030209815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Semiconductor device and its manufacturing method'
[patent_app_type] => new
[patent_app_number] => 10/430189
[patent_app_country] => US
[patent_app_date] => 2003-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 44
[patent_no_of_words] => 8355
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20030209815.pdf
[firstpage_image] =>[orig_patent_app_number] => 10430189
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/430189 | Semiconductor device and its manufacturing method | May 6, 2003 | Abandoned |
Array
(
[id] => 7317865
[patent_doc_number] => 20040224473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Using metal peatures to align etches of compound semiconductors'
[patent_app_type] => new
[patent_app_number] => 10/430499
[patent_app_country] => US
[patent_app_date] => 2003-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3130
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20040224473.pdf
[firstpage_image] =>[orig_patent_app_number] => 10430499
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/430499 | Using metal peatures to align etches of compound semiconductors | May 5, 2003 | Abandoned |
Array
(
[id] => 507725
[patent_doc_number] => 07202514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Self aligned compact bipolar junction transistor layout and method of making same'
[patent_app_type] => utility
[patent_app_number] => 10/418395
[patent_app_country] => US
[patent_app_date] => 2003-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3471
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/202/07202514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10418395
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/418395 | Self aligned compact bipolar junction transistor layout and method of making same | Apr 16, 2003 | Issued |
Array
(
[id] => 686647
[patent_doc_number] => 07078314
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-07-18
[patent_title] => 'Memory device having improved periphery and core isolation'
[patent_app_type] => utility
[patent_app_number] => 10/407999
[patent_app_country] => US
[patent_app_date] => 2003-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 33
[patent_no_of_words] => 8646
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/078/07078314.pdf
[firstpage_image] =>[orig_patent_app_number] => 10407999
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/407999 | Memory device having improved periphery and core isolation | Apr 2, 2003 | Issued |
Array
(
[id] => 6865275
[patent_doc_number] => 20030190801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'Method for forming a metal extrusion free via'
[patent_app_type] => new
[patent_app_number] => 10/404491
[patent_app_country] => US
[patent_app_date] => 2003-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2732
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20030190801.pdf
[firstpage_image] =>[orig_patent_app_number] => 10404491
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/404491 | Method for forming a metal extrusion free via | Mar 31, 2003 | Abandoned |
Array
(
[id] => 1165565
[patent_doc_number] => 06756305
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-29
[patent_title] => 'Stacked dice bonded with aluminum posts'
[patent_app_type] => B1
[patent_app_number] => 10/405789
[patent_app_country] => US
[patent_app_date] => 2003-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 3943
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/756/06756305.pdf
[firstpage_image] =>[orig_patent_app_number] => 10405789
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/405789 | Stacked dice bonded with aluminum posts | Mar 31, 2003 | Issued |
Array
(
[id] => 7438090
[patent_doc_number] => 20040050319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'Nickel-silicon compound forming method, semiconductor device manufacturing method, and semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/405999
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4260
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0050/20040050319.pdf
[firstpage_image] =>[orig_patent_app_number] => 10405999
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/405999 | Nickel-silicon compound forming method, semiconductor device manufacturing method, and semiconductor device | Mar 30, 2003 | Abandoned |
Array
(
[id] => 1053171
[patent_doc_number] => 06858499
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-22
[patent_title] => 'Method for fabrication of MOSFET with buried gate'
[patent_app_type] => utility
[patent_app_number] => 10/404989
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 1685
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/858/06858499.pdf
[firstpage_image] =>[orig_patent_app_number] => 10404989
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/404989 | Method for fabrication of MOSFET with buried gate | Mar 30, 2003 | Issued |
Array
(
[id] => 1130360
[patent_doc_number] => 06787415
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-07
[patent_title] => 'Nonvolatile memory with pedestals'
[patent_app_type] => B1
[patent_app_number] => 10/402698
[patent_app_country] => US
[patent_app_date] => 2003-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3493
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/787/06787415.pdf
[firstpage_image] =>[orig_patent_app_number] => 10402698
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/402698 | Nonvolatile memory with pedestals | Mar 27, 2003 | Issued |
Array
(
[id] => 7343946
[patent_doc_number] => 20040191937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'BARRIER LAYERS FOR MICROELECTROMECHANICAL SYSTEMS'
[patent_app_type] => new
[patent_app_number] => 10/402789
[patent_app_country] => US
[patent_app_date] => 2003-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12991
[patent_no_of_claims] => 63
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20040191937.pdf
[firstpage_image] =>[orig_patent_app_number] => 10402789
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/402789 | Barrier layers for microelectromechanical systems | Mar 27, 2003 | Issued |
Array
(
[id] => 1110914
[patent_doc_number] => 06806140
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-19
[patent_title] => 'Semiconductor memory device for eliminating floating body effect and method of fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 10/401972
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 4798
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/806/06806140.pdf
[firstpage_image] =>[orig_patent_app_number] => 10401972
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/401972 | Semiconductor memory device for eliminating floating body effect and method of fabricating the same | Mar 26, 2003 | Issued |
Array
(
[id] => 1112933
[patent_doc_number] => 06803291
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-12
[patent_title] => 'Method to preserve alignment mark optical integrity'
[patent_app_type] => B1
[patent_app_number] => 10/394089
[patent_app_country] => US
[patent_app_date] => 2003-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 4654
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/803/06803291.pdf
[firstpage_image] =>[orig_patent_app_number] => 10394089
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/394089 | Method to preserve alignment mark optical integrity | Mar 19, 2003 | Issued |
Array
(
[id] => 1168668
[patent_doc_number] => 06753231
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-22
[patent_title] => 'Semiconductor integrated circuit and method for manufacturing the same'
[patent_app_type] => B2
[patent_app_number] => 10/379543
[patent_app_country] => US
[patent_app_date] => 2003-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 29
[patent_no_of_words] => 11227
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 345
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/753/06753231.pdf
[firstpage_image] =>[orig_patent_app_number] => 10379543
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/379543 | Semiconductor integrated circuit and method for manufacturing the same | Mar 5, 2003 | Issued |
Array
(
[id] => 6865276
[patent_doc_number] => 20030190802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'Method for forming a plug metal layer'
[patent_app_type] => new
[patent_app_number] => 10/376309
[patent_app_country] => US
[patent_app_date] => 2003-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4150
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20030190802.pdf
[firstpage_image] =>[orig_patent_app_number] => 10376309
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/376309 | Method for forming a plug metal layer | Mar 2, 2003 | Issued |
Array
(
[id] => 1216534
[patent_doc_number] => 06706630
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-16
[patent_title] => 'Method for forming an alloyed metal conductive element of an integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 10/376399
[patent_app_country] => US
[patent_app_date] => 2003-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2798
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/706/06706630.pdf
[firstpage_image] =>[orig_patent_app_number] => 10376399
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/376399 | Method for forming an alloyed metal conductive element of an integrated circuit | Feb 27, 2003 | Issued |
Array
(
[id] => 1062820
[patent_doc_number] => 06849564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-01
[patent_title] => '1R1D R-RAM array with floating p-well'
[patent_app_type] => utility
[patent_app_number] => 10/376796
[patent_app_country] => US
[patent_app_date] => 2003-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2822
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/849/06849564.pdf
[firstpage_image] =>[orig_patent_app_number] => 10376796
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/376796 | 1R1D R-RAM array with floating p-well | Feb 26, 2003 | Issued |
Array
(
[id] => 6725198
[patent_doc_number] => 20030207510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-06
[patent_title] => 'Semiconductor device, and its manufacturing method, circuit substrate, and electronic apparatus'
[patent_app_type] => new
[patent_app_number] => 10/370699
[patent_app_country] => US
[patent_app_date] => 2003-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5359
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20030207510.pdf
[firstpage_image] =>[orig_patent_app_number] => 10370699
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/370699 | Semiconductor device, and its manufacturing method, circuit substrate, and electronic apparatus | Feb 23, 2003 | Issued |
Array
(
[id] => 7383342
[patent_doc_number] => 20040029329
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Method for transferring and stacking of semiconductor devices'
[patent_app_type] => new
[patent_app_number] => 10/372548
[patent_app_country] => US
[patent_app_date] => 2003-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6018
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20040029329.pdf
[firstpage_image] =>[orig_patent_app_number] => 10372548
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/372548 | Method for transferring and stacking of semiconductor devices | Feb 20, 2003 | Issued |
Array
(
[id] => 6834767
[patent_doc_number] => 20030162313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Method for sawing wafer'
[patent_app_type] => new
[patent_app_number] => 10/366299
[patent_app_country] => US
[patent_app_date] => 2003-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2576
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20030162313.pdf
[firstpage_image] =>[orig_patent_app_number] => 10366299
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/366299 | Method for sawing wafer | Feb 11, 2003 | Issued |