
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6843221
[patent_doc_number] => 20030148568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Flash memory device and fabrication process thereof, method of forming a dielectric film'
[patent_app_type] => new
[patent_app_number] => 10/359701
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[pdf_file] => publications/A1/0148/20030148568.pdf
[firstpage_image] =>[orig_patent_app_number] => 10359701
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/359701 | Flash memory device and fabrication process thereof, method of forming a dielectric film | Feb 6, 2003 | Issued |
Array
(
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[patent_doc_number] => 20030137007
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[patent_issue_date] => 2003-07-24
[patent_title] => 'Flash memory device and fabrication process thereof, method of forming a dielectric film'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/359592 | Flash memory device and fabrication process thereof, method of forming a dielectric film | Feb 6, 2003 | Issued |
Array
(
[id] => 6843282
[patent_doc_number] => 20030148629
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[patent_issue_date] => 2003-08-07
[patent_title] => 'Flash memory device and fabrication process thereof, method of forming a dielectric film'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/359714 | Flash memory device and fabrication process thereof, method of forming a dielectric film | Feb 6, 2003 | Issued |
Array
(
[id] => 1216490
[patent_doc_number] => 06706613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-16
[patent_title] => 'Methods for manufacturing stacked gates including oxide/nitride/oxide (ONO) interlayer dielectrics using pre-annealing and/or post-annealing in nitrogen'
[patent_app_type] => B2
[patent_app_number] => 10/359789
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/359789 | Methods for manufacturing stacked gates including oxide/nitride/oxide (ONO) interlayer dielectrics using pre-annealing and/or post-annealing in nitrogen | Feb 5, 2003 | Issued |
Array
(
[id] => 737375
[patent_doc_number] => 07033957
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-04-25
[patent_title] => 'ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/358586
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/358586 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Feb 4, 2003 | Issued |
Array
(
[id] => 7287296
[patent_doc_number] => 20040147092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'METHOD FOR FABRICATING THIN FILM TRANSISTOR DISPLAY DEVICE'
[patent_app_type] => new
[patent_app_number] => 10/353180
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[firstpage_image] =>[orig_patent_app_number] => 10353180
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/353180 | Method for fabricating thin film transistor display device | Jan 27, 2003 | Issued |
Array
(
[id] => 1202740
[patent_doc_number] => 06720269
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-13
[patent_title] => 'Semiconductor device having a self-aligned contact structure and methods of forming the same'
[patent_app_type] => B2
[patent_app_number] => 10/347219
[patent_app_country] => US
[patent_app_date] => 2003-01-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/720/06720269.pdf
[firstpage_image] =>[orig_patent_app_number] => 10347219
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/347219 | Semiconductor device having a self-aligned contact structure and methods of forming the same | Jan 20, 2003 | Issued |
Array
(
[id] => 6706440
[patent_doc_number] => 20030153174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-14
[patent_title] => 'Methods for making a paste of materials to form bumps for screen print processes'
[patent_app_type] => new
[patent_app_number] => 10/346280
[patent_app_country] => US
[patent_app_date] => 2003-01-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/346280 | Methods for making a paste of materials to form bumps for screen print processes | Jan 16, 2003 | Issued |
Array
(
[id] => 436193
[patent_doc_number] => 07262451
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-28
[patent_title] => 'High performance embedded DRAM technology with strained silicon'
[patent_app_type] => utility
[patent_app_number] => 10/541660
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10541660
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/541660 | High performance embedded DRAM technology with strained silicon | Jan 7, 2003 | Issued |
Array
(
[id] => 1071862
[patent_doc_number] => 06841446
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-11
[patent_title] => 'Fabrication method for a flash memory device'
[patent_app_type] => utility
[patent_app_number] => 10/338999
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338999 | Fabrication method for a flash memory device | Jan 7, 2003 | Issued |
Array
(
[id] => 7295901
[patent_doc_number] => 20040124466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'METHOD FOR FABRICATING PROGRAMMABLE MEMORY ARRAY STRUCTURES INCORPORATING SERIES-CONNECTED TRANSISTOR STRINGS'
[patent_app_type] => new
[patent_app_number] => 10/335089
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0124/20040124466.pdf
[firstpage_image] =>[orig_patent_app_number] => 10335089
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/335089 | Method for fabricating programmable memory array structures incorporating series-connected transistor strings | Dec 30, 2002 | Issued |
Array
(
[id] => 6843241
[patent_doc_number] => 20030148588
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[patent_issue_date] => 2003-08-07
[patent_title] => 'Process for manufacturing low-cost and high-quality SOI substrates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/331189 | Process for manufacturing low-cost and high-quality SOI substrates | Dec 25, 2002 | Issued |
Array
(
[id] => 6787777
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[patent_title] => 'Capacitor and manufacturing method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/311999 | Capacitor and manufacturing method thereof | Dec 22, 2002 | Issued |
Array
(
[id] => 563098
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[patent_title] => 'Angled wafer rotating ion implantation'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/323889 | Angled wafer rotating ion implantation | Dec 19, 2002 | Issued |
Array
(
[id] => 1130522
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[patent_title] => 'Method for forming a plug metal layer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/320473 | Method for forming a plug metal layer | Dec 16, 2002 | Issued |
Array
(
[id] => 7305018
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[patent_title] => 'Using an electron beam to write phase change memory devices'
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Array
(
[id] => 491444
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313887 | CMOS inverters configured using multiple-gate transistors | Dec 5, 2002 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/309547 | Semiconductor memory device for reducing damage to interlevel dielectric layer and fabrication method thereof | Dec 2, 2002 | Issued |
Array
(
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[firstpage_image] =>[orig_patent_app_number] => 10306789
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/306789 | Optical device, method of manufacturing the same, optical module, circuit board and electronic instrument | Nov 26, 2002 | Issued |