Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6817894 [patent_doc_number] => 20030068852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Protective film for the fabrication of direct build-up layers on an encapsulated die package' [patent_app_type] => new [patent_app_number] => 10/299135 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 4310 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068852.pdf [firstpage_image] =>[orig_patent_app_number] => 10299135 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299135
Protective film for the fabrication of direct build-up layers on an encapsulated die package Nov 18, 2002 Abandoned
Array ( [id] => 6799472 [patent_doc_number] => 20030094636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Semiconductor device and method of manufacturing same' [patent_app_type] => new [patent_app_number] => 10/294625 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094636.pdf [firstpage_image] =>[orig_patent_app_number] => 10294625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/294625
Semiconductor device and method of manufacturing same Nov 14, 2002 Issued
Array ( [id] => 7400694 [patent_doc_number] => 20040023484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'METHOD OF DEEP CONTACT FILL AND PLANARIZATION FOR DUAL DAMASCENE STRUCTURES' [patent_app_type] => new [patent_app_number] => 10/292589 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2442 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023484.pdf [firstpage_image] =>[orig_patent_app_number] => 10292589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292589
Method of deep contact fill and planarization for dual damascene structures Nov 12, 2002 Issued
Array ( [id] => 1172711 [patent_doc_number] => 06750129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Process for forming fusible links' [patent_app_type] => B2 [patent_app_number] => 10/292399 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2852 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750129.pdf [firstpage_image] =>[orig_patent_app_number] => 10292399 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292399
Process for forming fusible links Nov 11, 2002 Issued
Array ( [id] => 1209404 [patent_doc_number] => 06713389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method of forming an electronic device' [patent_app_type] => B2 [patent_app_number] => 10/290988 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 24867 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713389.pdf [firstpage_image] =>[orig_patent_app_number] => 10290988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290988
Method of forming an electronic device Nov 7, 2002 Issued
Array ( [id] => 6671852 [patent_doc_number] => 20030057455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/285790 [patent_app_country] => US [patent_app_date] => 2002-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5617 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20030057455.pdf [firstpage_image] =>[orig_patent_app_number] => 10285790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/285790
SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same Oct 31, 2002 Issued
Array ( [id] => 7629802 [patent_doc_number] => 06818554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method for fabricating a semiconductor device having a metallic silicide layer' [patent_app_type] => B2 [patent_app_number] => 10/283189 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818554.pdf [firstpage_image] =>[orig_patent_app_number] => 10283189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283189
Method for fabricating a semiconductor device having a metallic silicide layer Oct 29, 2002 Issued
Array ( [id] => 6781052 [patent_doc_number] => 20030062499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Electro-optical device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/282689 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 22675 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062499.pdf [firstpage_image] =>[orig_patent_app_number] => 10282689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282689
Electro-optical device and manufacturing method thereof Oct 28, 2002 Issued
Array ( [id] => 6817890 [patent_doc_number] => 20030068848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'MFOS memory transistor' [patent_app_type] => new [patent_app_number] => 10/282533 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3159 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068848.pdf [firstpage_image] =>[orig_patent_app_number] => 10282533 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282533
MFOS memory transistor Oct 27, 2002 Abandoned
Array ( [id] => 6720913 [patent_doc_number] => 20030054602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => ' Semiconductor Processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry' [patent_app_type] => new [patent_app_number] => 10/280452 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2906 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054602.pdf [firstpage_image] =>[orig_patent_app_number] => 10280452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/280452
SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY Oct 24, 2002 Issued
Array ( [id] => 1134086 [patent_doc_number] => 06784039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method to form self-aligned split gate flash with L-shaped wordline spacers' [patent_app_type] => B2 [patent_app_number] => 10/272086 [patent_app_country] => US [patent_app_date] => 2002-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784039.pdf [firstpage_image] =>[orig_patent_app_number] => 10272086 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/272086
Method to form self-aligned split gate flash with L-shaped wordline spacers Oct 15, 2002 Issued
Array ( [id] => 6747283 [patent_doc_number] => 20030041803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Semiconductor device, a method of manufacturing the semiconductor device, and an apparatus for manufacturing the semiconductor device' [patent_app_type] => new [patent_app_number] => 10/270189 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 19599 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20030041803.pdf [firstpage_image] =>[orig_patent_app_number] => 10270189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270189
Semiconductor device, a method of manufacturing the semiconductor device, and an apparatus for manufacturing the semiconductor device Oct 14, 2002 Abandoned
Array ( [id] => 6692722 [patent_doc_number] => 20030040154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Novel DRAM access transistor' [patent_app_type] => new [patent_app_number] => 10/270150 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3084 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040154.pdf [firstpage_image] =>[orig_patent_app_number] => 10270150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270150
DRAM access transistor Oct 14, 2002 Issued
Array ( [id] => 6720912 [patent_doc_number] => 20030054601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Lateral heterojunction bipolar transistor and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/269079 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8887 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054601.pdf [firstpage_image] =>[orig_patent_app_number] => 10269079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269079
Lateral heterojunction bipolar transistor and method of fabricating the same Oct 10, 2002 Issued
Array ( [id] => 6720911 [patent_doc_number] => 20030054600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Semiconductor memory device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/267698 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054600.pdf [firstpage_image] =>[orig_patent_app_number] => 10267698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/267698
Semiconductor memory device and method of fabricating the same Oct 9, 2002 Abandoned
Array ( [id] => 7264147 [patent_doc_number] => 20040241987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion' [patent_app_type] => new [patent_app_number] => 10/466299 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 10647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241987.pdf [firstpage_image] =>[orig_patent_app_number] => 10466299 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/466299
Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion Oct 7, 2002 Issued
Array ( [id] => 1281106 [patent_doc_number] => 06646288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Electro-optical device and electronic equipment' [patent_app_type] => B2 [patent_app_number] => 10/263709 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 59 [patent_no_of_words] => 22968 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646288.pdf [firstpage_image] =>[orig_patent_app_number] => 10263709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263709
Electro-optical device and electronic equipment Oct 3, 2002 Issued
Array ( [id] => 6651201 [patent_doc_number] => 20030008451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Contactless channel write/erase flash memory cell and its fabrication method' [patent_app_type] => new [patent_app_number] => 10/065189 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3594 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008451.pdf [firstpage_image] =>[orig_patent_app_number] => 10065189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065189
Contactless channel write/erase flash memory cell and its fabrication method Sep 24, 2002 Issued
Array ( [id] => 6773215 [patent_doc_number] => 20030016553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Vertically stacked field programmable nonvolatile memory and method of fabrication' [patent_app_type] => new [patent_app_number] => 10/251206 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14428 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20030016553.pdf [firstpage_image] =>[orig_patent_app_number] => 10251206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/251206
Vertically stacked field programmable nonvolatile memory and method of fabrication Sep 18, 2002 Issued
Array ( [id] => 7964333 [patent_doc_number] => 06680260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method of producing a bonded wafer and the bonded wafer' [patent_app_type] => B2 [patent_app_number] => 10/244412 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10619 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680260.pdf [firstpage_image] =>[orig_patent_app_number] => 10244412 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/244412
Method of producing a bonded wafer and the bonded wafer Sep 16, 2002 Issued
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