Search

David Vu

Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2048
Issued Applications
1711
Pending Applications
95
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7677566 [patent_doc_number] => 20040152260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Non-volatile memory cell with non-uniform surface floating gate and control gate' [patent_app_type] => new [patent_app_number] => 09/948612 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3056 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152260.pdf [firstpage_image] =>[orig_patent_app_number] => 09948612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948612
Non-volatile memory cell with non-uniform surface floating gate and control gate Sep 6, 2001 Abandoned
Array ( [id] => 6750563 [patent_doc_number] => 20030045083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Low cost microelectronic circuit package' [patent_app_type] => new [patent_app_number] => 09/946749 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4630 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045083.pdf [firstpage_image] =>[orig_patent_app_number] => 09946749 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946749
Low cost microelectronic circuit package Sep 4, 2001 Issued
Array ( [id] => 1398813 [patent_doc_number] => 06537875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor memory device for reducing damage to interlevel dielectric layer and fabrication method thereof' [patent_app_type] => B2 [patent_app_number] => 09/947189 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 7788 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537875.pdf [firstpage_image] =>[orig_patent_app_number] => 09947189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947189
Semiconductor memory device for reducing damage to interlevel dielectric layer and fabrication method thereof Sep 4, 2001 Issued
Array ( [id] => 6060425 [patent_doc_number] => 20020030287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Resistance-reducing conductive adhesives for attachment of electronic components' [patent_app_type] => new [patent_app_number] => 09/946689 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3968 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20020030287.pdf [firstpage_image] =>[orig_patent_app_number] => 09946689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946689
Resistance-reducing conductive adhesives for attachment of electronic components Sep 3, 2001 Issued
Array ( [id] => 6095894 [patent_doc_number] => 20020052088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Method of manufacturing photomask, photomask, and method of manufacturing semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 09/943499 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15266 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052088.pdf [firstpage_image] =>[orig_patent_app_number] => 09943499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943499
Method of manufacturing photomask, photomask, and method of manufacturing semiconductor integrated circuit device Aug 30, 2001 Issued
Array ( [id] => 1516170 [patent_doc_number] => 06420760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-16 [patent_title] => 'Thin film transistor manufacturing method and thin film transistor' [patent_app_type] => B2 [patent_app_number] => 09/941980 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3593 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420760.pdf [firstpage_image] =>[orig_patent_app_number] => 09941980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941980
Thin film transistor manufacturing method and thin film transistor Aug 28, 2001 Issued
Array ( [id] => 6750529 [patent_doc_number] => 20030045049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Method of forming chalcogenide comprising devices' [patent_app_type] => new [patent_app_number] => 09/943199 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3980 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045049.pdf [firstpage_image] =>[orig_patent_app_number] => 09943199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943199
Method of forming chalcogenide comprising devices Aug 28, 2001 Issued
Array ( [id] => 556885 [patent_doc_number] => 07157314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Vertically stacked field programmable nonvolatile memory and method of fabrication' [patent_app_type] => utility [patent_app_number] => 09/939498 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 14389 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157314.pdf [firstpage_image] =>[orig_patent_app_number] => 09939498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939498
Vertically stacked field programmable nonvolatile memory and method of fabrication Aug 23, 2001 Issued
Array ( [id] => 556885 [patent_doc_number] => 07157314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Vertically stacked field programmable nonvolatile memory and method of fabrication' [patent_app_type] => utility [patent_app_number] => 09/939498 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 14389 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157314.pdf [firstpage_image] =>[orig_patent_app_number] => 09939498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939498
Vertically stacked field programmable nonvolatile memory and method of fabrication Aug 23, 2001 Issued
Array ( [id] => 1416683 [patent_doc_number] => 06509255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same' [patent_app_type] => B2 [patent_app_number] => 09/935971 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5115 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509255.pdf [firstpage_image] =>[orig_patent_app_number] => 09935971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935971
Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same Aug 22, 2001 Issued
Array ( [id] => 1581172 [patent_doc_number] => 06423620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY DRAM CIRCUITRY' [patent_app_type] => B1 [patent_app_number] => 09/935474 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 2968 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423620.pdf [firstpage_image] =>[orig_patent_app_number] => 09935474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935474
SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY DRAM CIRCUITRY Aug 20, 2001 Issued
Array ( [id] => 1332527 [patent_doc_number] => 06596625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method and device for producing a metal/metal contact in a multilayer metallization of an integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/932899 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4595 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596625.pdf [firstpage_image] =>[orig_patent_app_number] => 09932899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932899
Method and device for producing a metal/metal contact in a multilayer metallization of an integrated circuit Aug 19, 2001 Issued
Array ( [id] => 6446945 [patent_doc_number] => 20020177249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method for manufacturing an LCD panel' [patent_app_type] => new [patent_app_number] => 09/930789 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1736 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177249.pdf [firstpage_image] =>[orig_patent_app_number] => 09930789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930789
Method for manufacturing an LCD panel Aug 14, 2001 Issued
Array ( [id] => 6934490 [patent_doc_number] => 20010055834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Method of making semiconductor packages at wafer level' [patent_app_type] => new [patent_app_number] => 09/925688 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2214 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055834.pdf [firstpage_image] =>[orig_patent_app_number] => 09925688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925688
Method of making semiconductor packages at wafer level Aug 9, 2001 Issued
Array ( [id] => 675765 [patent_doc_number] => 07087493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-08 [patent_title] => 'Memory with 6T small aspect ratio cells having metal—1 elements physically connected to metal—0 elements' [patent_app_type] => utility [patent_app_number] => 09/921394 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 12835 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087493.pdf [firstpage_image] =>[orig_patent_app_number] => 09921394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921394
Memory with 6T small aspect ratio cells having metal—1 elements physically connected to metal—0 elements Aug 1, 2001 Issued
Array ( [id] => 7636607 [patent_doc_number] => 06380048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Die paddle enhancement for exposed pad in semiconductor packaging' [patent_app_type] => B1 [patent_app_number] => 09/920599 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6093 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380048.pdf [firstpage_image] =>[orig_patent_app_number] => 09920599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920599
Die paddle enhancement for exposed pad in semiconductor packaging Aug 1, 2001 Issued
Array ( [id] => 1409958 [patent_doc_number] => 06534813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Semiconductor device having a self-aligned contact structure and methods of forming the same' [patent_app_type] => B1 [patent_app_number] => 09/889588 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 11897 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534813.pdf [firstpage_image] =>[orig_patent_app_number] => 09889588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/889588
Semiconductor device having a self-aligned contact structure and methods of forming the same Aug 1, 2001 Issued
Array ( [id] => 7395161 [patent_doc_number] => 20040038496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method and system for bonding a semiconductor chip onto a carrier using micro-pins' [patent_app_type] => new [patent_app_number] => 10/333199 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6342 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038496.pdf [firstpage_image] =>[orig_patent_app_number] => 10333199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/333199
Method and system for bonding a semiconductor chip onto a carrier using micro-pins Jul 25, 2001 Issued
Array ( [id] => 6032992 [patent_doc_number] => 20020019096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Silicon on insulator transistor structure for imbedded DRAM' [patent_app_type] => new [patent_app_number] => 09/915989 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2397 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019096.pdf [firstpage_image] =>[orig_patent_app_number] => 09915989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915989
Silicon on insulator transistor structure for imbedded DRAM Jul 25, 2001 Abandoned
Array ( [id] => 1306878 [patent_doc_number] => 06617258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same' [patent_app_type] => B1 [patent_app_number] => 09/911289 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617258.pdf [firstpage_image] =>[orig_patent_app_number] => 09911289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911289
Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same Jul 22, 2001 Issued
Menu