David Vu

Array ( [id] => 1336434 [patent_doc_number] => 06593227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method and apparatus for planarizing surfaces of semiconductor device conductive layers' [patent_app_type] => B1 [patent_app_number] => 09/851199 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3814 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593227.pdf [firstpage_image] =>[orig_patent_app_number] => 09851199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6048264 [patent_doc_number] => 20020168880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Method for cleaning polysilicon' [patent_app_type] => new [patent_app_number] => 09/851699 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2292 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20020168880.pdf [firstpage_image] =>[orig_patent_app_number] => 09851699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5968539 [patent_doc_number] => 20020090799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Substrate grinding systems and methods to reduce dot depth variation' [patent_app_type] => new [patent_app_number] => 09/851500 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7846 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20020090799.pdf [firstpage_image] =>[orig_patent_app_number] => 09851500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459331 [patent_doc_number] => 06391707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method of manufacturing a zero mask high density metal/insulator/metal capacitor' [patent_app_type] => B1 [patent_app_number] => 09/849299 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 8074 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391707.pdf [firstpage_image] =>[orig_patent_app_number] => 09849299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6894040 [patent_doc_number] => 20010016406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry' [patent_app_type] => new [patent_app_number] => 09/848863 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2906 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016406.pdf [firstpage_image] =>[orig_patent_app_number] => 09848863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1449972 [patent_doc_number] => 06455382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Multi-step method for forming sacrificial silicon oxide layer' [patent_app_type] => B1 [patent_app_number] => 09/848599 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 8163 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455382.pdf [firstpage_image] =>[orig_patent_app_number] => 09848599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6409293 [patent_doc_number] => 20020182852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method for reducing micro-masking defects in trench isolation regions' [patent_app_type] => new [patent_app_number] => 09/849389 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2071 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182852.pdf [firstpage_image] =>[orig_patent_app_number] => 09849389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1570193 [patent_doc_number] => 06498062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'DRAM access transistor' [patent_app_type] => B2 [patent_app_number] => 09/842788 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 3037 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498062.pdf [firstpage_image] =>[orig_patent_app_number] => 09842788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602559 [patent_doc_number] => 06432738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Single-layer-electrode type two-phase charge coupled device having smooth charge transfer' [patent_app_type] => B1 [patent_app_number] => 09/842999 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 3365 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432738.pdf [firstpage_image] =>[orig_patent_app_number] => 09842999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1597781 [patent_doc_number] => 06492682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method of producing a bonded wafer and the bonded wafer' [patent_app_type] => B1 [patent_app_number] => 09/830389 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10580 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492682.pdf [firstpage_image] =>[orig_patent_app_number] => 09830389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6378922 [patent_doc_number] => 20020119628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'STI method for semiconductor processes' [patent_app_type] => new [patent_app_number] => 09/840999 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2015 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20020119628.pdf [firstpage_image] =>[orig_patent_app_number] => 09840999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585562 [patent_doc_number] => 06358826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Device improvement by lowering LDD resistance with new spacer/silicide process' [patent_app_type] => B1 [patent_app_number] => 09/838389 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6006 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358826.pdf [firstpage_image] =>[orig_patent_app_number] => 09838389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1600575 [patent_doc_number] => 06475924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Substrate and process for producing the same' [patent_app_type] => B2 [patent_app_number] => 09/838089 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 12266 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475924.pdf [firstpage_image] =>[orig_patent_app_number] => 09838089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6176664 [patent_doc_number] => 20020155654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Vertical gate top engineering for improved GC and CB process windows' [patent_app_type] => new [patent_app_number] => 09/837799 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155654.pdf [firstpage_image] =>[orig_patent_app_number] => 09837799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6095892 [patent_doc_number] => 20020052086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Semiconductor device and method of manufacturing same' [patent_app_type] => new [patent_app_number] => 09/832889 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052086.pdf [firstpage_image] =>[orig_patent_app_number] => 09832889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4378185 [patent_doc_number] => 06303477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Removal of organic anti-reflection coatings in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/826489 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3216 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303477.pdf [firstpage_image] =>[orig_patent_app_number] => 826489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6111495 [patent_doc_number] => 20020173160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Plasma etching of organic antireflective coating' [patent_app_type] => new [patent_app_number] => 09/820689 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173160.pdf [firstpage_image] =>[orig_patent_app_number] => 09820689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423876 [patent_doc_number] => 06515297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'CVD-SiC self-supporting membrane structure and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/821689 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3513 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515297.pdf [firstpage_image] =>[orig_patent_app_number] => 09821689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1270062 [patent_doc_number] => 06653179 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method for manufacturing a thin film semiconductor device, method for manufacturing a display device, method for manufacturing a thin film transistors, and method for forming a semiconductor thin film' [patent_app_type] => B1 [patent_app_number] => 09/743899 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 45 [patent_no_of_words] => 12434 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653179.pdf [firstpage_image] =>[orig_patent_app_number] => 09743899 [rel_patent_id] =>[rel_patent_doc_number] =>)