
David Vu
Examiner (ID: 8926, Phone: (571)272-1798 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2048 |
| Issued Applications | 1711 |
| Pending Applications | 95 |
| Abandoned Applications | 268 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1125250
[patent_doc_number] => 06794714
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-21
[patent_title] => 'Transistor and method for fabricating the same'
[patent_app_type] => B2
[patent_app_number] => 09/751939
[patent_app_country] => US
[patent_app_date] => 2001-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 26
[patent_no_of_words] => 2725
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/794/06794714.pdf
[firstpage_image] =>[orig_patent_app_number] => 09751939
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/751939 | Transistor and method for fabricating the same | Jan 1, 2001 | Issued |
Array
(
[id] => 7093177
[patent_doc_number] => 20010034104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-25
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/739499
[patent_app_country] => US
[patent_app_date] => 2000-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2218
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20010034104.pdf
[firstpage_image] =>[orig_patent_app_number] => 09739499
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/739499 | Method for manufacturing semiconductor device | Dec 19, 2000 | Issued |
Array
(
[id] => 1545252
[patent_doc_number] => 06444545
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Device structure for storing charge and method therefore'
[patent_app_type] => B1
[patent_app_number] => 09/740249
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3122
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/444/06444545.pdf
[firstpage_image] =>[orig_patent_app_number] => 09740249
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/740249 | Device structure for storing charge and method therefore | Dec 18, 2000 | Issued |
Array
(
[id] => 6889413
[patent_doc_number] => 20010024868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-27
[patent_title] => 'Microelectronic structure and method of fabricating it'
[patent_app_type] => new
[patent_app_number] => 09/729069
[patent_app_country] => US
[patent_app_date] => 2000-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5851
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20010024868.pdf
[firstpage_image] =>[orig_patent_app_number] => 09729069
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/729069 | Microelectronic structure and method of fabricating it | Dec 3, 2000 | Abandoned |
Array
(
[id] => 1532563
[patent_doc_number] => 06410415
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Flip chip mounting technique'
[patent_app_type] => B1
[patent_app_number] => 09/724019
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 12360
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/410/06410415.pdf
[firstpage_image] =>[orig_patent_app_number] => 09724019
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/724019 | Flip chip mounting technique | Nov 27, 2000 | Issued |
Array
(
[id] => 1565765
[patent_doc_number] => 06376310
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Fabrication method of nonvolatile memory device'
[patent_app_type] => B1
[patent_app_number] => 09/722659
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 4388
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/376/06376310.pdf
[firstpage_image] =>[orig_patent_app_number] => 09722659
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/722659 | Fabrication method of nonvolatile memory device | Nov 27, 2000 | Issued |
Array
(
[id] => 7636550
[patent_doc_number] => 06380106
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures'
[patent_app_type] => B1
[patent_app_number] => 09/721719
[patent_app_country] => US
[patent_app_date] => 2000-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2863
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/380/06380106.pdf
[firstpage_image] =>[orig_patent_app_number] => 09721719
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/721719 | Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures | Nov 26, 2000 | Issued |
Array
(
[id] => 1424374
[patent_doc_number] => 06507086
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-14
[patent_title] => 'Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same'
[patent_app_type] => B1
[patent_app_number] => 09/715679
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5086
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/507/06507086.pdf
[firstpage_image] =>[orig_patent_app_number] => 09715679
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715679 | Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same | Nov 16, 2000 | Issued |
Array
(
[id] => 1341180
[patent_doc_number] => 06586279
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'Method of integrating a heat spreader and a semiconductor, and package formed thereby'
[patent_app_type] => B1
[patent_app_number] => 09/715360
[patent_app_country] => US
[patent_app_date] => 2000-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2700
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/586/06586279.pdf
[firstpage_image] =>[orig_patent_app_number] => 09715360
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/715360 | Method of integrating a heat spreader and a semiconductor, and package formed thereby | Nov 16, 2000 | Issued |
Array
(
[id] => 1097445
[patent_doc_number] => 06822304
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Sputtered silicon for microstructures and microcavities'
[patent_app_type] => B1
[patent_app_number] => 09/710489
[patent_app_country] => US
[patent_app_date] => 2000-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 5586
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/822/06822304.pdf
[firstpage_image] =>[orig_patent_app_number] => 09710489
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/710489 | Sputtered silicon for microstructures and microcavities | Nov 9, 2000 | Issued |
Array
(
[id] => 1421030
[patent_doc_number] => 06509588
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-21
[patent_title] => 'Method for interconnecting anodes and cathodes in a flat capacitor'
[patent_app_type] => B1
[patent_app_number] => 09/706519
[patent_app_country] => US
[patent_app_date] => 2000-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 5442
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/509/06509588.pdf
[firstpage_image] =>[orig_patent_app_number] => 09706519
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706519 | Method for interconnecting anodes and cathodes in a flat capacitor | Nov 2, 2000 | Issued |
Array
(
[id] => 1559755
[patent_doc_number] => 06436783
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-20
[patent_title] => 'Method of forming MOS transistor'
[patent_app_type] => B1
[patent_app_number] => 09/664059
[patent_app_country] => US
[patent_app_date] => 2000-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 15642
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/436/06436783.pdf
[firstpage_image] =>[orig_patent_app_number] => 09664059
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/664059 | Method of forming MOS transistor | Sep 17, 2000 | Issued |
Array
(
[id] => 1416061
[patent_doc_number] => 06518149
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 09/657185
[patent_app_country] => US
[patent_app_date] => 2000-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 7439
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/518/06518149.pdf
[firstpage_image] =>[orig_patent_app_number] => 09657185
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/657185 | Semiconductor device and method of manufacturing the same | Sep 6, 2000 | Issued |
Array
(
[id] => 1536147
[patent_doc_number] => 06337265
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-08
[patent_title] => 'Method for integration of integrated circuit devices'
[patent_app_type] => B1
[patent_app_number] => 09/653369
[patent_app_country] => US
[patent_app_date] => 2000-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2733
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/337/06337265.pdf
[firstpage_image] =>[orig_patent_app_number] => 09653369
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/653369 | Method for integration of integrated circuit devices | Aug 31, 2000 | Issued |
| 09/653319 | Memory cell structure of flash memory having circumventing floating gate and method for fabricating the same | Aug 31, 2000 | Abandoned |
Array
(
[id] => 1544213
[patent_doc_number] => 06373087
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses'
[patent_app_type] => B1
[patent_app_number] => 09/652479
[patent_app_country] => US
[patent_app_date] => 2000-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3970
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/373/06373087.pdf
[firstpage_image] =>[orig_patent_app_number] => 09652479
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652479 | Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses | Aug 30, 2000 | Issued |
Array
(
[id] => 1415398
[patent_doc_number] => 06518097
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Method for fabricating wafer-level flip chip package using pre-coated anisotropic conductive adhesive'
[patent_app_type] => B1
[patent_app_number] => 09/650709
[patent_app_country] => US
[patent_app_date] => 2000-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2547
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/518/06518097.pdf
[firstpage_image] =>[orig_patent_app_number] => 09650709
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/650709 | Method for fabricating wafer-level flip chip package using pre-coated anisotropic conductive adhesive | Aug 28, 2000 | Issued |
Array
(
[id] => 1370933
[patent_doc_number] => 06562641
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-13
[patent_title] => 'Apparatus and methods of semiconductor packages having circuit-bearing interconnect components'
[patent_app_type] => B1
[patent_app_number] => 09/644196
[patent_app_country] => US
[patent_app_date] => 2000-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4347
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/562/06562641.pdf
[firstpage_image] =>[orig_patent_app_number] => 09644196
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/644196 | Apparatus and methods of semiconductor packages having circuit-bearing interconnect components | Aug 21, 2000 | Issued |
Array
(
[id] => 1440159
[patent_doc_number] => 06495476
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-17
[patent_title] => 'Method for preventing native oxide growth during nitridation'
[patent_app_type] => B1
[patent_app_number] => 09/642939
[patent_app_country] => US
[patent_app_date] => 2000-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1500
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/495/06495476.pdf
[firstpage_image] =>[orig_patent_app_number] => 09642939
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/642939 | Method for preventing native oxide growth during nitridation | Aug 21, 2000 | Issued |
Array
(
[id] => 4324340
[patent_doc_number] => 06329219
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Method of processing a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/644249
[patent_app_country] => US
[patent_app_date] => 2000-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 4732
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/329/06329219.pdf
[firstpage_image] =>[orig_patent_app_number] => 644249
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/644249 | Method of processing a semiconductor device | Aug 21, 2000 | Issued |