David W. Duffy

Array ( [id] => 17676911 [patent_doc_number] => 20220190078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/512926 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17870872 [patent_doc_number] => 20220293609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/452272 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17403014 [patent_doc_number] => 20220045105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => DISPLAY DEVICE INCLUDING POLYCRYSTALLINE SILICON LAYER, METHOD OF MANUFACTURING POLYCRYSTALLINE SILICON LAYER, AND METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/510995 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17403101 [patent_doc_number] => 20220045192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METAL OXIDE INTERLAYER STRUCTURE FOR nFET AND pFET [patent_app_type] => utility [patent_app_number] => 17/508595 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17737958 [patent_doc_number] => 20220223420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/505678 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19705044 [patent_doc_number] => 12199091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Shallow trench isolation processing with local oxidation of silicon [patent_app_type] => utility [patent_app_number] => 17/503877 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 6464 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20347552 [patent_doc_number] => 12471290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Ferroelectric device and semiconductor device [patent_app_type] => utility [patent_app_number] => 18/030334 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 102 [patent_no_of_words] => 61935 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18030334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18823096 [patent_doc_number] => 20230397437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/249415 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18249415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19046455 [patent_doc_number] => 11935574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Memory cells and methods of forming a capacitor including current leakage paths having different total resistances [patent_app_type] => utility [patent_app_number] => 17/496564 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7337 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17523040 [patent_doc_number] => 20220108889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => METHODS FOR DEPOSITING III-ALLOYS ON SUBSTRATES AND COMPOSITIONS THEREFROM [patent_app_type] => utility [patent_app_number] => 17/495913 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18791180 [patent_doc_number] => 20230380175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/031421 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17373673 [patent_doc_number] => 20220028725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => MANUFACTURING OF CAVITIES [patent_app_type] => utility [patent_app_number] => 17/496411 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20455899 [patent_doc_number] => 12518959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Method for manufacturing wafer having functional film [patent_app_type] => utility [patent_app_number] => 18/030549 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5879 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18030549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19858405 [patent_doc_number] => 12261259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Light-emitting chip and light-emitting substrate [patent_app_type] => utility [patent_app_number] => 17/481326 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7495 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18224940 [patent_doc_number] => 20230063934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 17/463726 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18317601 [patent_doc_number] => 11631685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/412291 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3843 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20496605 [patent_doc_number] => 12538495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor device, capacitor, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/023618 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 127 [patent_no_of_words] => 56180 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18023618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18131287 [patent_doc_number] => 11557504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Semiconductor device including isolation layers and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/410149 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 38 [patent_no_of_words] => 10813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18068264 [patent_doc_number] => 20220399352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => FERROELECTRIC RANDOM ACCESS MEMORY (FRAM) CAPACITORS AND METHODS OF CONSTRUCTION [patent_app_type] => utility [patent_app_number] => 17/409883 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18248965 [patent_doc_number] => 11605561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Backside metal removal die singulation systems and related methods [patent_app_type] => utility [patent_app_number] => 17/445632 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445632 [rel_patent_id] =>[rel_patent_doc_number] =>)