Search

David W. Duffy

Examiner (ID: 16996, Phone: (571)272-1574 , Office: P/3716 )

Most Active Art Unit
3716
Art Unit(s)
3715, 3714, 3700, 3716
Total Applications
560
Issued Applications
295
Pending Applications
17
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20063553 [patent_doc_number] => 20250201775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => HIGH CAPACITANCE HYBRID BONDED CAPACITOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/544114 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544114
HIGH CAPACITANCE HYBRID BONDED CAPACITOR DEVICE Dec 17, 2023 Pending
Array ( [id] => 19253032 [patent_doc_number] => 20240204029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => IMAGE ACQUISITION DEVICE [patent_app_type] => utility [patent_app_number] => 18/536511 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536511
IMAGE ACQUISITION DEVICE Dec 11, 2023 Pending
Array ( [id] => 20053834 [patent_doc_number] => 20250192056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/534948 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534948
SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME Dec 10, 2023 Pending
Array ( [id] => 19068910 [patent_doc_number] => 20240103336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => LASER PROCESSING DEVICE, LASER PROCESSING METHOD, AND ELECTRONIC DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/533238 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533238
LASER PROCESSING DEVICE, LASER PROCESSING METHOD, AND ELECTRONIC DEVICE MANUFACTURING METHOD Dec 7, 2023 Pending
Array ( [id] => 19073321 [patent_doc_number] => 20240107747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => Array of Memory Cells, Methods Used in Forming an Array of Memory Cells, Methods Used in Forming an Array of Vertical Transistors, Methods Used in Forming an Array of Vertical Transistors, and Methods Used in Forming an Array of Capacitors [patent_app_type] => utility [patent_app_number] => 18/533574 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533574
Array of memory cells, methods used in forming an array of memory cells, methods used in forming an array of vertical transistors, and methods used in forming an array of capacitors Dec 7, 2023 Issued
Array ( [id] => 19335736 [patent_doc_number] => 20240250166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/533354 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533354 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533354
TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Dec 7, 2023 Pending
Array ( [id] => 19577389 [patent_doc_number] => 20240381681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => ELECTRONIC APPARATUSES AND MANUFACTURING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/533229 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533229
ELECTRONIC APPARATUSES AND MANUFACTURING METHODS THEREOF Dec 7, 2023 Pending
Array ( [id] => 20047115 [patent_doc_number] => 20250185337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => SEMICONDUCTOR STRUCTURE WITH TWO AIR GAPS ON TWO SIDES OF A TOP SOURCE-DRAIN MIDDLE-OF-LINE CONTACT VIA [patent_app_type] => utility [patent_app_number] => 18/529195 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529195
SEMICONDUCTOR STRUCTURE WITH TWO AIR GAPS ON TWO SIDES OF A TOP SOURCE-DRAIN MIDDLE-OF-LINE CONTACT VIA Dec 4, 2023 Pending
Array ( [id] => 20047130 [patent_doc_number] => 20250185352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => INTEGRATION OF A VERTICAL DIODE AND A TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/529077 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529077
INTEGRATION OF A VERTICAL DIODE AND A TRANSISTOR Dec 4, 2023 Pending
Array ( [id] => 19321635 [patent_doc_number] => 20240243182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => MICROELECTRONIC DEVICE AND METHOD OF FORMING [patent_app_type] => utility [patent_app_number] => 18/527484 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527484
MICROELECTRONIC DEVICE AND METHOD OF FORMING Dec 3, 2023 Pending
Array ( [id] => 19828834 [patent_doc_number] => 12249630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Method for manufacturing a grid [patent_app_type] => utility [patent_app_number] => 18/526516 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526516
Method for manufacturing a grid Nov 30, 2023 Issued
Array ( [id] => 20625933 [patent_doc_number] => 12593458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/526454 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 7525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526454
Semiconductor device Nov 30, 2023 Issued
Array ( [id] => 19038392 [patent_doc_number] => 20240088207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => CAPACITANCE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/510787 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510787 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510787
Capacitance structure Nov 15, 2023 Issued
Array ( [id] => 20021726 [patent_doc_number] => 20250159948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SPLIT SUPPORT SHIELD STRUCTURES FOR TRENCHED SEMICONDUCTOR DEVICES WITH INTEGRATED SCHOTTKY DIODES [patent_app_type] => utility [patent_app_number] => 18/508322 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508322
SPLIT SUPPORT SHIELD STRUCTURES FOR TRENCHED SEMICONDUCTOR DEVICES WITH INTEGRATED SCHOTTKY DIODES Nov 13, 2023 Pending
Array ( [id] => 19176223 [patent_doc_number] => 20240162197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SCALABLE POWER SEMICONDUCTOR DEVICE PACKAGE WITH LOW INDUCTANCE [patent_app_type] => utility [patent_app_number] => 18/508551 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508551
SCALABLE POWER SEMICONDUCTOR DEVICE PACKAGE WITH LOW INDUCTANCE Nov 13, 2023 Pending
Array ( [id] => 20082534 [patent_doc_number] => 12356631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => FeRAM with laminated ferroelectric film and method forming same [patent_app_type] => utility [patent_app_number] => 18/386649 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 3156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386649 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386649
FeRAM with laminated ferroelectric film and method forming same Nov 2, 2023 Issued
Array ( [id] => 20004883 [patent_doc_number] => 20250143105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DISPLAY PANELS AND DISPLAY DEVICES [patent_app_type] => utility [patent_app_number] => 18/565102 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18565102 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/565102
DISPLAY PANELS AND DISPLAY DEVICES Nov 1, 2023 Pending
Array ( [id] => 19409123 [patent_doc_number] => 20240292634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MEMORY DEVICE WITH INTERPLANE PAD PART [patent_app_type] => utility [patent_app_number] => 18/499446 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499446
MEMORY DEVICE WITH INTERPLANE PAD PART Oct 31, 2023 Pending
Array ( [id] => 20004701 [patent_doc_number] => 20250142923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR DEVICE WITH MULTI-STEP GATE AND RECESSED MULTI-STEP FIELD PLATE AND METHOD OF FABRICATION THEREFOR [patent_app_type] => utility [patent_app_number] => 18/499088 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499088
SEMICONDUCTOR DEVICE WITH MULTI-STEP GATE AND RECESSED MULTI-STEP FIELD PLATE AND METHOD OF FABRICATION THEREFOR Oct 30, 2023 Pending
Array ( [id] => 19193535 [patent_doc_number] => 20240172448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => 3D FERROELECTRIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/492130 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492130
3D FERROELECTRIC MEMORY DEVICE Oct 22, 2023 Pending
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