Search

David W. Duffy

Examiner (ID: 16996, Phone: (571)272-1574 , Office: P/3716 )

Most Active Art Unit
3716
Art Unit(s)
3715, 3714, 3700, 3716
Total Applications
560
Issued Applications
295
Pending Applications
17
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20553200 [patent_doc_number] => 12564014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Method and apparatus for substrate temperature control [patent_app_type] => utility [patent_app_number] => 18/093139 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093139
Method and apparatus for substrate temperature control Jan 3, 2023 Issued
Array ( [id] => 18745592 [patent_doc_number] => 20230354586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/149750 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149750
Semiconductor structure and manufacturing method thereof Jan 3, 2023 Issued
Array ( [id] => 19288032 [patent_doc_number] => 20240224515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => STRUCTURE WITH BURIED DOPED REGION FOR COUPLING SOURCE LINE CONTACT TO GATE STRUCTURE OF MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/149733 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149733
STRUCTURE WITH BURIED DOPED REGION FOR COUPLING SOURCE LINE CONTACT TO GATE STRUCTURE OF MEMORY CELL Jan 3, 2023 Pending
Array ( [id] => 20597912 [patent_doc_number] => 12581649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Semiconductor device, fabrication method, and memory system [patent_app_type] => utility [patent_app_number] => 18/092109 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 7956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092109
Semiconductor device, fabrication method, and memory system Dec 29, 2022 Issued
Array ( [id] => 20509021 [patent_doc_number] => 12543313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Semiconductor structure and its fabrication method, memory and memory system [patent_app_type] => utility [patent_app_number] => 18/091146 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091146
Semiconductor structure and its fabrication method, memory and memory system Dec 28, 2022 Issued
Array ( [id] => 19271527 [patent_doc_number] => 20240215234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/090931 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090931
Memory devices and methods for forming the same Dec 28, 2022 Issued
Array ( [id] => 19271511 [patent_doc_number] => 20240215218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/088944 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088944 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088944
Semiconductor structure and forming method thereof Dec 26, 2022 Issued
Array ( [id] => 20217618 [patent_doc_number] => 12414287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Method of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 18/088370 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 3057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088370 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088370
Method of fabricating semiconductor device Dec 22, 2022 Issued
Array ( [id] => 18336029 [patent_doc_number] => 20230127978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => METHOD OF FABRICATING SUPER-JUNCTION BASED VERTICAL GALLIUM NITRIDE JFET AND MOSFET POWER DEVICES [patent_app_type] => utility [patent_app_number] => 18/085985 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085985
Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices Dec 20, 2022 Issued
Array ( [id] => 20552930 [patent_doc_number] => 12563738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/069398 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 5197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/069398
Semiconductor devices Dec 20, 2022 Issued
Array ( [id] => 18322098 [patent_doc_number] => 20230120226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR DEVICE HAVING A MAIN TRANSISTOR, A SENSE TRANSISTOR, AND A BYPASS DIODE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/085756 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085756
Semiconductor device having a main transistor, a sense transistor, and a bypass diode structure Dec 20, 2022 Issued
Array ( [id] => 18323834 [patent_doc_number] => 20230121962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/083927 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083927 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/083927
Semiconductor device and method for manufacturing same Dec 18, 2022 Issued
Array ( [id] => 18336577 [patent_doc_number] => 20230128526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME [patent_app_type] => utility [patent_app_number] => 18/068438 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068438 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068438
Doped polar layers and semiconductor device incorporating same Dec 18, 2022 Issued
Array ( [id] => 18394995 [patent_doc_number] => 20230163216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME [patent_app_type] => utility [patent_app_number] => 18/067653 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067653
Doped polar layers and semiconductor device incorporating same Dec 15, 2022 Issued
Array ( [id] => 19079636 [patent_doc_number] => 11949017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Doped polar layers and semiconductor device incorporating same [patent_app_type] => utility [patent_app_number] => 18/067633 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 26399 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067633
Doped polar layers and semiconductor device incorporating same Dec 15, 2022 Issued
Array ( [id] => 20540189 [patent_doc_number] => 12557276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Memory device and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/082048 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4579 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082048 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/082048
Memory device and method of forming the same Dec 14, 2022 Issued
Array ( [id] => 19208002 [patent_doc_number] => 20240179901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD FOR IMPROVED YIELD AND RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/082080 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/082080
Three-dimensional memory device and fabrication method for improved yield and reliability Dec 14, 2022 Issued
Array ( [id] => 18696371 [patent_doc_number] => 20230326809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => STANDARD WAFERS, METHOD OF MAKING THE SAME AND CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 18/066145 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066145
STANDARD WAFERS, METHOD OF MAKING THE SAME AND CALIBRATION METHOD Dec 13, 2022 Abandoned
Array ( [id] => 18890991 [patent_doc_number] => 11869768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Method of forming transition metal dichalcogenide thin film [patent_app_type] => utility [patent_app_number] => 18/063909 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6892 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063909 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063909
Method of forming transition metal dichalcogenide thin film Dec 8, 2022 Issued
Array ( [id] => 20276440 [patent_doc_number] => 12446229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Semiconductor device including ferroelectric layer [patent_app_type] => utility [patent_app_number] => 18/063938 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3243 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063938
Semiconductor device including ferroelectric layer Dec 8, 2022 Issued
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