Search

De'maris R Brown

Examiner (ID: 4353)

Most Active Art Unit
2437
Art Unit(s)
CSDE, 2437
Total Applications
45
Issued Applications
29
Pending Applications
0
Abandoned Applications
16

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9613563 [patent_doc_number] => 20140203420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE PRODUCED USING PRODUCTION METHOD' [patent_app_type] => utility [patent_app_number] => 14/239014 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5217 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14239014 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/239014
Method for producing semiconductor device Sep 11, 2012 Issued
Array ( [id] => 8910002 [patent_doc_number] => 08482067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates to achieve a high drain-to-body breakdown voltage, a method of forming the transistor and a program storage device for designing the transistor' [patent_app_type] => utility [patent_app_number] => 13/604671 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 13889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604671 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604671
Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates to achieve a high drain-to-body breakdown voltage, a method of forming the transistor and a program storage device for designing the transistor Sep 5, 2012 Issued
Array ( [id] => 9034410 [patent_doc_number] => 20130237048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'METHOD OF FABRICATING ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/602404 [patent_app_country] => US [patent_app_date] => 2012-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3294 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602404 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602404
Method of fabricating erasable programmable single-poly nonvolatile memory Sep 3, 2012 Issued
Array ( [id] => 9338986 [patent_doc_number] => 20140065768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'METHOD FOR PROCESSING A WAFER AND METHOD FOR DICING A WAFER' [patent_app_type] => utility [patent_app_number] => 13/602219 [patent_app_country] => US [patent_app_date] => 2012-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6192 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602219 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602219
Method for processing a wafer and method for dicing a wafer Sep 2, 2012 Issued
Array ( [id] => 9950998 [patent_doc_number] => 08999784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Methods of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/602104 [patent_app_country] => US [patent_app_date] => 2012-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4414 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602104 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602104
Methods of manufacturing semiconductor device Aug 31, 2012 Issued
Array ( [id] => 9041760 [patent_doc_number] => 20130244398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/601805 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2759 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601805 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601805
Method of manufacturing semiconductor memory device Aug 30, 2012 Issued
Array ( [id] => 8519804 [patent_doc_number] => 20120319212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'SRAM Structure with FinFETs Having Multiple Fins' [patent_app_type] => utility [patent_app_number] => 13/598093 [patent_app_country] => US [patent_app_date] => 2012-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13598093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/598093
SRAM structure with FinFETs having multiple fins Aug 28, 2012 Issued
Array ( [id] => 9869688 [patent_doc_number] => 08957463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Gate tunable tunnel diode' [patent_app_type] => utility [patent_app_number] => 13/597610 [patent_app_country] => US [patent_app_date] => 2012-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 5609 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13597610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/597610
Gate tunable tunnel diode Aug 28, 2012 Issued
Array ( [id] => 9330652 [patent_doc_number] => 20140057434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'THROUGH SILICON VIA PROCESS' [patent_app_type] => utility [patent_app_number] => 13/593517 [patent_app_country] => US [patent_app_date] => 2012-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3750 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13593517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/593517
Through silicon via process Aug 23, 2012 Issued
Array ( [id] => 9496458 [patent_doc_number] => 08735271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Gate tunable tunnel diode' [patent_app_type] => utility [patent_app_number] => 13/594037 [patent_app_country] => US [patent_app_date] => 2012-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 5551 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13594037 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/594037
Gate tunable tunnel diode Aug 23, 2012 Issued
Array ( [id] => 8708043 [patent_doc_number] => 20130065332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'METHOD FOR MANUFACTURING LED WITH AN ENCAPSULANT HAVING A FLAT TOP FACE' [patent_app_type] => utility [patent_app_number] => 13/593473 [patent_app_country] => US [patent_app_date] => 2012-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1706 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13593473 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/593473
METHOD FOR MANUFACTURING LED WITH AN ENCAPSULANT HAVING A FLAT TOP FACE Aug 22, 2012 Abandoned
Array ( [id] => 9389178 [patent_doc_number] => 08685775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Group III nitride semiconductor light-emitting device and production method therefor' [patent_app_type] => utility [patent_app_number] => 13/593240 [patent_app_country] => US [patent_app_date] => 2012-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5238 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13593240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/593240
Group III nitride semiconductor light-emitting device and production method therefor Aug 22, 2012 Issued
Array ( [id] => 9330603 [patent_doc_number] => 20140057385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'III-V PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/593138 [patent_app_country] => US [patent_app_date] => 2012-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4448 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13593138 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/593138
III-V PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD Aug 22, 2012 Abandoned
Array ( [id] => 8671053 [patent_doc_number] => 20130045591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'NEGATIVE TONE DEVELOP PROCESS WITH PHOTORESIST DOPING' [patent_app_type] => utility [patent_app_number] => 13/585924 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1344 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13585924 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/585924
NEGATIVE TONE DEVELOP PROCESS WITH PHOTORESIST DOPING Aug 14, 2012 Abandoned
Array ( [id] => 8821584 [patent_doc_number] => 20130122629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'SYSTEMS, METHODS AND PRODUCTS INCLUDING FEATURES OF LASER IRRADIATION AND/OR CLEAVING OF SILICON WITH OTHER SUBSTRATES OR LAYERS' [patent_app_type] => utility [patent_app_number] => 13/572258 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4259 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572258 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572258
SYSTEMS, METHODS AND PRODUCTS INCLUDING FEATURES OF LASER IRRADIATION AND/OR CLEAVING OF SILICON WITH OTHER SUBSTRATES OR LAYERS Aug 9, 2012 Abandoned
Array ( [id] => 8502659 [patent_doc_number] => 20120302067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'Methods of Etching Trenches into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes' [patent_app_type] => utility [patent_app_number] => 13/570583 [patent_app_country] => US [patent_app_date] => 2012-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 3430 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13570583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/570583
Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes Aug 8, 2012 Issued
Array ( [id] => 8499702 [patent_doc_number] => 20120299110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights' [patent_app_type] => utility [patent_app_number] => 13/562805 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4245 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562805 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562805
Dielectric punch-through stoppers for forming FinFETs having dual fin heights Jul 30, 2012 Issued
Array ( [id] => 9613536 [patent_doc_number] => 20140203393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/239375 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7609 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14239375 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/239375
Semiconductor device Jul 30, 2012 Issued
Array ( [id] => 8499735 [patent_doc_number] => 20120299142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'PHOTOELECTRIC CONVERSION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/558790 [patent_app_country] => US [patent_app_date] => 2012-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7032 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558790 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/558790
PHOTOELECTRIC CONVERSION DEVICE Jul 25, 2012 Abandoned
Array ( [id] => 9768124 [patent_doc_number] => 20140291786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'component having a micromechanical microphone structure' [patent_app_type] => utility [patent_app_number] => 14/233969 [patent_app_country] => US [patent_app_date] => 2012-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3554 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14233969 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/233969
component having a micromechanical microphone structure Jul 19, 2012 Abandoned
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