De'maris R Brown

Array ( [id] => 6202499 [patent_doc_number] => 20110065285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'DIELECTRIC LAYER STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/949739 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2881 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20110065285.pdf [firstpage_image] =>[orig_patent_app_number] => 12949739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9010014 [patent_doc_number] => 08525316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Eutectic flow containment in a semiconductor fabrication process' [patent_app_type] => utility [patent_app_number] => 12/914859 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 16 [patent_no_of_words] => 4112 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12914859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8159400 [patent_doc_number] => 20120100685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS' [patent_app_type] => utility [patent_app_number] => 12/908306 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20120100685.pdf [firstpage_image] =>[orig_patent_app_number] => 12908306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8139789 [patent_doc_number] => 20120094450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'MANUFACTURING METHOD OF MULTI-LEVEL CELL NOR FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 12/907077 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2084 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20120094450.pdf [firstpage_image] =>[orig_patent_app_number] => 12907077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8435460 [patent_doc_number] => 08283229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Methods of fabricating vertical channel transistors' [patent_app_type] => utility [patent_app_number] => 12/906630 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 110 [patent_no_of_words] => 13215 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12906630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8875685 [patent_doc_number] => 08470650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Semiconductor device and manufacturing method for the same' [patent_app_type] => utility [patent_app_number] => 12/906553 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 71 [patent_no_of_words] => 37471 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12906553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8139827 [patent_doc_number] => 20120094465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'INTEGRATED PLANAR AND MULTIPLE GATE FETS' [patent_app_type] => utility [patent_app_number] => 12/905575 [patent_app_country] => US [patent_app_date] => 2010-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20120094465.pdf [firstpage_image] =>[orig_patent_app_number] => 12905575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7784301 [patent_doc_number] => 20120045857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/905258 [patent_app_country] => US [patent_app_date] => 2010-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4159 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20120045857.pdf [firstpage_image] =>[orig_patent_app_number] => 12905258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10858230 [patent_doc_number] => 08884434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Method and system for improving reliability of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/890721 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3972 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8690454 [patent_doc_number] => 08389983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Organic light emitting apparatus and method of manufacturing organic light emitting apparatus' [patent_app_type] => utility [patent_app_number] => 12/890104 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6208362 [patent_doc_number] => 20110133285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'SRAM Structure with FinFETs Having Multiple Fins' [patent_app_type] => utility [patent_app_number] => 12/890132 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133285.pdf [firstpage_image] =>[orig_patent_app_number] => 12890132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6027017 [patent_doc_number] => 20110079878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER' [patent_app_type] => utility [patent_app_number] => 12/890219 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079878.pdf [firstpage_image] =>[orig_patent_app_number] => 12890219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8049639 [patent_doc_number] => 20120074562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Three-Dimensional Integrated Circuit Structure with Low-K Materials' [patent_app_type] => utility [patent_app_number] => 12/890094 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074562.pdf [firstpage_image] =>[orig_patent_app_number] => 12890094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8049641 [patent_doc_number] => 20120074559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE USING THROUGH SUBSTRATE VIAS TO GROUND LID' [patent_app_type] => utility [patent_app_number] => 12/889586 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074559.pdf [firstpage_image] =>[orig_patent_app_number] => 12889586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9324046 [patent_doc_number] => 08659072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Series FinFET implementation schemes' [patent_app_type] => utility [patent_app_number] => 12/890084 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2172 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8049707 [patent_doc_number] => 20120074581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 12/890082 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10885 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074581.pdf [firstpage_image] =>[orig_patent_app_number] => 12890082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6026757 [patent_doc_number] => 20110079783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'ARRAY SUBSTRATE FOR ORGANIC ELECTROLUMINESCENT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/890112 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079783.pdf [firstpage_image] =>[orig_patent_app_number] => 12890112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8049713 [patent_doc_number] => 20120074588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/890338 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074588.pdf [firstpage_image] =>[orig_patent_app_number] => 12890338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6075378 [patent_doc_number] => 20110140268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PACKAGE STRUCTURES, AND PROCESSES OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 12/890345 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6290 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140268.pdf [firstpage_image] =>[orig_patent_app_number] => 12890345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8049653 [patent_doc_number] => 20120074560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/890161 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074560.pdf [firstpage_image] =>[orig_patent_app_number] => 12890161 [rel_patent_id] =>[rel_patent_doc_number] =>)